video: find5: reduce dsi pll lock times
Setting dsi pll ctrl reg 16 and 17 to optimal values to reduce lock
time from 8ms to less than 1ms.

Reference commit: TeamEOS/kernel_asus_flo@f55a6b5

Change-Id: Ibe71390c0f5806f155f6bf9b2687b695b773ca05
display: find5: enable TE vsync function
1. Enable TE vsync function in gpio config.
   Note that pinfo.lcd.refx100 need to be align with TE frequency in panel.
2. add lcd vertical porches to have correct value of MDP register 0x100
   and 0x210
3. remove the mfd->ibuf.vsync_enable in condition to have correct value of
   MDP register 0x20c

case 01186196
Bug: 8767597

Change-Id: Ie8c3021d447c255c811ca95bf71ec4cfb2949b6f
Signed-off-by: yetta_wu <yetta_wu@asus.com>

Note: without mfd->ibuf.vsync_enable