btor
makefile
Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
splitnet -driver feature

Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor
BTOR backend
Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor
width issues
dff cell for more than one registers
slice error corrected
Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor
Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor
verilog default options pull
shift operator width issues
pmux2mux
Fixed a type in $mem model in simlib.v
More changes to simlib to make it friendlier to a wider range of tools
Fixed parsing of verilog macros at end of line
Fixed $lut simlib model for a wider range of tools
Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor
script added
Added Verilog parser support for asserts