draw: don't use clipvertex output if user plane clipping is disabled

The non-llvm path made sure that both clip and pre_clip_pos point to the data
output by position, not clipvertex, if user based clipping is disabled.
However, the llvm path did not, which apparently led to failures if
gl_ClipVertex was written but user plane clipping not enabled (bug 80183).
Why I have no idea really, but just make it match the non-llvm behavior...

Reviewed-by: Brian Paul <brianp@vmware.com>
draw: (trivial) use information about gs being present from variant key

This is a purely cosmetic change.

Reviewed-by: Brian Paul <brianp@vmware.com>
vc4: Initial skeleton driver import.

This mostly just takes every draw call and turns it into a sequence of
commands that clear the FBO and draw a single shaded triangle to it,
regardless of the actual input vertices or shaders.  I copied the initial
driver skeleton mostly from freedreno, and I've preserved Rob Clark's
copyright for those.  I also based my initial hardcoded shaders and
command lists on Scott Mansell (phire)'s "hackdriver" project, though the
bit patterns of the shaders emitted end up being different.

v2: Rebase on gallium megadrivers changes.
v3: Rebase on PIPE_SHADER_CAP_MAX_CONSTS change.
v4: Rely on simpenrose actually being installed when building for
    simulation.
v5: Add more header duplicate-include guards.
v6: Apply Emil's review (protection against vc4 sim and ilo at the same
    time, and dropping the dricommon drm bits) and fix a copyright header
    (thanks, Roland)
vc4: Start converting the driver to use vertex shaders.

Note: This is the cutoff point where I switched from developing primarily
on the Pi to developing o the simulator.  As a result, from this point on
the code is untested on the Pi (the kernel code I have currently wasn't
rendering anything at this commit, though the simulator renders
successfully, suggesting kernel bugs).
vc4: Switch to actually generating vertex and fragment shader code from TGSI.

This introduces an IR (QIR, for QPU IR) to do optimization on.  It's a
scalar, SSA IR in general.  It looks like optimization is pretty easy this
way, though I haven't figured out if it's going to be good for our weird
register allocation or not (or if I want to reduce to basically QPU
instructions first), and I've got some problems with it having some
multi-QPU-instruction opcodes (SEQ and CMP, for example) which I probably
want to break down.

Of course, this commit mostly doesn't work, since many other things are
still hardwired, like the VBO data.

v2: Rewrite to use a bunch of helpers (qir_OPCODE) for emitting QIR
    instructions into temporary values, and make qir_inst4 take the 4 args
    separately instead of an array (all later callers wanted individual
    args).
vc4: Add initial support for math opcodes
vc4: Fix UBO allocation when no uniforms are used.

We do rely on a real BO getting allocated, so make sure we ask for a non-zero size.
vc4: Use the user's actual first vertex attribute.

This is hardcoded to read it as RGBA32F so far, but starts to get more
tests working.
vc4: Add support for SNE/SEQ/SGE/SLT.
vc4: Add VC4_DEBUG env option

v2: Fix an accidental deletion of some characters from the copyright
    message (caught by Ilia Mirkin)
vc4: Don't reallocate the tile alloc/state bos every frame.

This was a problem for the simulator since we don't free memory back to
it, and it would soon just run out.
vc4: Load the tile buffer before incrementally drawing.

We will want to occasionally disable this again when we do clear support.

v2: Squash with the previous commit (I accidentally committed at two
    stages of writing the change)
vc4: Add shader variant caching to handle FS output swizzle.
vc4: Fix emit of ABS

v2: Rebase on qir helpers.
vc4: Use r3 instead of r5 for temps, since r5 only has 32 bits of storage

Reserving a whole accumulator for temps is awful in the first place, but
I'll fix that later.
vc4: Add WIP support for varyings.

It doesn't do all the interpolation yet, but more tests can run now.

v2: Rebase on helpers.
vc4: Make scheduling of NOPs a separate step from QIR -> QPU translation.

This should also be used as a way to pair QIR instructions into QPU
instructions later.
vc4: Add support for CMP.

This took a couple of tries, and this is the squash of those attempts.

v2: Fix register file conflicts on the args in the
    destination-is-accumulator case.
v3: Rebase on helper change and qir_inst4 change.
vc4: Add an initial pass of algebraic optimization.

There was a lot of extra noise in my piglit shader dumps because of silly
CMPs.
vc4: Add dead code elimination.

This cleans up a bunch of noise in the compiled coordinate shaders (since
we don't need the varying outputs), and also from writemasked instructions
with negated src operands.