Started MC Composite. First step, how do we get the CPU ID in the
kernel? Answer: Save it in the TSS and push it onto stack when we get
into kernel.

Merge branch 'master' of https://github.com/gparmer/Composite

Conflicts:
	src/components/implementation/cbuf_c/naive/cbuf.c
	src/components/implementation/no_interface/connector/Makefile
	src/components/implementation/sched/base_case/base_case.c
	src/components/implementation/sched/cos_sched_base.c
	src/components/implementation/tests/unit_cbuf1/Makefile
	src/components/implementation/tests/unit_cbuf2/Makefile
	src/components/implementation/tests/unit_translator/Makefile
	src/components/interface/sched/stubs/s_stub.S
Merge branch 'master' of github.com:interwq/Composite

Conflicts:
	src/components/implementation/cbuf_c/naive/cbuf.c
	src/components/implementation/exe_cbuf_synth_hier/exe_cbuf_shbc/exe_cbuf_synth_basecase.c
	src/components/implementation/exe_cbuf_synth_hier/exe_cbuf_shrec/exe_cbuf_synth_hier.c
	src/components/implementation/no_interface/tmem_policy/tmem_policy.c
	src/components/implementation/sched/cos_sched_base.c
	src/components/implementation/tests/micro_ping_cbuf/Makefile
	src/components/implementation/tests/micro_ping_cbuf/micro_ping.c
	src/components/implementation/tests/micro_pong_cbuf/Makefile
	src/components/implementation/tests/micro_pong_cbuf/micro_pong.c
	src/components/implementation/tests/unit_cbuf1/Makefile
	src/components/implementation/tests/unit_cbuf2/Makefile
	src/components/implementation/tests/unit_translator/Makefile
	src/components/include/cbuf.h
	src/kernel/include/shared/cos_config.h
Multicore Composite update:

1) Invocation works finally. Now multiple threads running on multiple
cores are able to call from cos_loader to scheduler. In cos_loader the
first init thread forks new processes for other cores. New threads
will call scheduler and waiting there.

2) Modified some data structures in scheduler and hijack code to
support SMP.

3) Kernel per-core data structure is added. Corresponding operations
are added too. (per_cpu.c and per_cpu.h)

4) Kernel and user-level get_cpuid functions are added. (kernel:
get_cpuid(), user: cos_cpuid())

Have some issues with upcall functions.

Merge branch 'master' of https://github.com/gparmer/Composite

Conflicts:
	src/kernel/include/shared/cos_config.h
Modified data structures in fp_rr and cos_sched_base to support
multicore. Going to change another two files.
Going to merge with Gabe's code base. We need the low-level booter for SMP support.
Merged with Gabe's code base which includes the low-level
booter. Changed the data-structure of llbooter to support SMP. Going
to add the booting code for SMP.

Merge branch 'master' of https://github.com/gparmer/Composite

Conflicts:
	src/components/implementation/mem_mgr/naive/mem_man.c
	src/components/implementation/no_interface/boot/booter.c
	src/components/implementation/no_interface/exe_cbuf_periodic/exe_cbuf_periodic.c
	src/components/implementation/sched/cos_sched_base.c
	src/components/implementation/tests/micro_ping_cbuf/micro_ping.c
	src/kernel/inv.c
Integrated with low-level booter - now we can boot Composite with
SMP. System can boot and run with no problem. Each core has their own
timer threads. All the booter loaded components / threads are assigned
to core 0, i.e. not changed yet. But I don't see why we can't
partition or schedule them to multicore, which we are really
interested in.

Got some issues with printc. Next I'm going to change the current
printc implementation to a low-level print implementation, which gets
rid of the shared region between components.
Implemented a new low-level printc component, which doesn't require
shared region between components for passing the string. Instead, we
use only 4 registers (4 parameters) as medium. Thus we need to call
llprintc component multiple times. Of course this will effect print
performance, but we need to get rid of the shared region.

Tested the llprintc with two timer threads. Worked well!

Going to change the trans print component.
Updated prints and the trans print component. It seems the print
function has some issue when printing in the timer thread. Gonna check
the cos print syscall.
Cleaned up the code. Fixed some issues of SMP system exiting
code. But need to work on that.
Implemented the booting up protocol between cores: the init core calls
llbooter first and does the loading and init work, then returns to
cos_loader and creates processes for other cores. After that all cores
call llbooter to run.

Also fixed an issue in the printc client code.
Fixed the children processes faulting on exit issue. Now the init core
will return to Linux and then kill all the children processes since
the children cannot return to their original processes as the
component 0 has only 1 pgd which points to the parent process. Tested
and it worked!
Cleaned up code. Next is the membrane, which will be interesting!
Implemented a prototype of the membrane. In the sched_base, now the
default threads are distributed evenly across cores. Tested with 4
cores enabled and worked well.
Changed the cacheline size to the correct value (64). Fixed a bug in
the request stack path when using cpuid.
Implemented a first step of IPI syscall. The syscall makes use of
Linux smp_call function. Currently it's not fast yet.(around 2200
cycles) Going to measure the cost further and see how much we can do.

Also, fixed a problem that children processes cannot return to their
original pgd. (Thanks Gabe!) Now the SMP system is re-runnable.
Did some measurements of IPIs. Will remove the benchmark code later.
Fixed a issue that clobbers registers when call brand_wait
syscall. Now all the registers are saved in the user space before
calling syscall. So we only need to make sure the IP and SP are
saved and restored appropriately.

The IPI syscall is very stable now - I tried calling it millions of
times and everything looks good. However I only tested with single
caller and single receiver. Will test multicore calling at the same
time next.
Tested multi-core(sender) to one core IPI. IPIs are delivered
correctly with two cores sending to one core. Some issue with the
memory consistency needs to be solved.
Fixed the python script of setting SMP affinity. Tested multi-sender
IPIs.