[C++11] Replace llvm::next and llvm::prior with std::next and std::prev.

Remove the old functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202636 91177308-0d34-0410-b5e6-96231b3b80d8
Test commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202641 91177308-0d34-0410-b5e6-96231b3b80d8
[C++11] Replace LLVM_STATIC_ASSERT with static_assert, we now have
access to it on all host toolchains.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202642 91177308-0d34-0410-b5e6-96231b3b80d8
[C++11] Replace llvm::tie with std::tie.

The old implementation is no longer needed in C++11.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202644 91177308-0d34-0410-b5e6-96231b3b80d8
Ensure bitcode encoding of instructions and their operands stays stable.
This includes instructions that relate to memory access (load/store/GEP), comparison instructions and calls.

Work was done by lama.saba@intel.com.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202647 91177308-0d34-0410-b5e6-96231b3b80d8
Add a PPC inline asm constraint type for single CR bits

Now that the PowerPC backend can track individual CR bits as first-class
registers, we should also have a way of allocating them for inline asm
statements. Because these registers are only one bit, if an output variable is
implicitly cast to a larger integer size, we'll get an any_extend to that
larger type (this is part of the existing target-independent logic). As a
result, regardless of the size of the output type, only the first bit is
meaningful.

The constraint identifier "wc" has been chosen for this purpose. Although gcc
does not currently support allocating individual CR bits, this identifier
choice has been coordinated with the gcc PowerPC team, and will be marked as
reserved for this purpose in the gcc constraints.md file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202657 91177308-0d34-0410-b5e6-96231b3b80d8
[Sparc] Add VIS instructions to sparc backend.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202660 91177308-0d34-0410-b5e6-96231b3b80d8
[Sparc] Add fcmpe* instructions to Sparc backend.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202661 91177308-0d34-0410-b5e6-96231b3b80d8
Give APInt move semantics.

The interaction between defaulted operators and move elision isn't
totally obvious, add a unit test so it doesn't break unintentionally.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202662 91177308-0d34-0410-b5e6-96231b3b80d8
[Sparc] Add support for decoding jmpl/retl/ret instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202663 91177308-0d34-0410-b5e6-96231b3b80d8
Remove unnecessary copy ctors.

They didn't provide any value over the default ones but blocked move semantics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202664 91177308-0d34-0410-b5e6-96231b3b80d8
[Sparc] Add return/rett instruction to Sparc backend.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202666 91177308-0d34-0410-b5e6-96231b3b80d8
[Sparc] Add trap on integer condition codes (Ticc) instructions to Sparc backend.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202670 91177308-0d34-0410-b5e6-96231b3b80d8