More CAEN COMS layout. Also did pulse inverter.

And began ribbon delay layout
Finished placing Ribbon Delay components.

They still need to be moved around though
Moved parts in ribbon delay around & added caps

Added bypass caps to the ribbon delay schematics. And moved
the pulldown resistors that were on the layout to better places.
Added those bypass caps to layout
Did layout for baseline monitoring
Began layout on delay then on tubii_time.

Had to stop though because the current package for the FOX CLOCK
is SIP6. Which cannot be right
Created packages and pad for the fox clock
Tubii_Clks layout and changed RefDes for some parts

Specifically for two MC10h104s in tubii_clks
Finished clock select layout.Changing 10h116 package

10h116 package was DIP now I'm gonna change it to PLCC everywhere
More Tubii Time layout. It's slow going.

I begin to question the feasability of the board.
I also question my ability to spell feasability
Tubii_time layout until I got to the jumperfield.

Need to figure out how to implement that