tcg-sparc: Fix ld64 for 32-bit mode

Since were not using an annulled branch, we need to put a nop
in the delay slot.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-sparc: Fix tlb read

We were computing the full address into %o0 and then not using it.
Adjust some of the computation to rely less on having to pull immediate
values into registers.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-sparc: Tidy call+jump patterns

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-sparc: Use intptr_t as appropriate

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-sparc: Don't handle remainder

The generic fallback is exactly what we implemented.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-sparc: Dont handle constant arguments to ext32 ops

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-sparc: Improve tcg_out_movi

If bits 31:13 are zero, reduce the insn count by one.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-sparc: Use TCGMemOp within qemu_ldst routines

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-sparc: Tidy tcg_out_tlb_load interface

Pass address registers explicitly, rather than as indicies of args[].
It's two argument registers either way.  Use more TCGReg as appropriate.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-sparc: Convert to new ldst helpers

All of the helpers with the explicit big/little endian option
require the return address as a parameter.  Acquire this via
a trampoline.

Move the load of areg0 into the trampoline.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-sparc: Convert to new ldst opcodes

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-sparc: Remove most uses of TCG_TARGET_REG_BITS

Replace with SPARC64 define.  Soon even sparcv8plus will use
64-bit register as far as TCG is concerned.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg: Fix missed pointer size != TCG_TARGET_REG_BITS changes

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg: Add INDEX_op_trunc_i32

Let the backend do something special for truncation.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-sparc: Support trunc_i32

Unlike a 64-bit shift op, allows the output to be in %l or %i registers
for sparcv8plus.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-sparc: Use 64-bit registers with sparcv8plus

Quite a lot of effort was spent composing and decomposing 64-bit
quantities in registers, when we should just create them and leave
them as one 64-bit register.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-sparc: Use the RETURN instruction

Saves one insn per TB exit over JMPL+RESTORE.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-sparc: Implement muls2_i32

Using the 32-bit SMUL is a tad more efficient than
resorting to extending and using the 64-bit MULX.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-sparc: Tidy check_fit_* tests

Use sextract instead of raw bit shifting for the tests.  Introduce
a new check_fit_ptr macro to make it clear we're looking at pointers.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-sparc: Don't handle mov/movi in tcg_out_op

Signed-off-by: Richard Henderson <rth@twiddle.net>