ARM: mvebu: Fix the operand list in the inline asm of armada_370_xp_pmsu_idle_enter

In the inline asm part of the function armada_370_xp_pmsu_idle_enter()
the input operand was used. The intent here was to let the compiler
choose this register so it could do the optimization it
needed.

However an input operand is not supposed to be modified by the inline
asm code. This can lead to improper generated instructions.

In some case generated instruction the compiler made the choice to
reuse the same register to store the return value. But in the assembly
part this register was modified, so it can lead to return an wrong
value.

The fix is to use a clobber. Thanks to this the compiler will know
that the value of this register will be modified.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: split again armada_370_xp_pmsu_idle_enter

do_armada_370_xp_cpu_suspend() and armada_370_xp_pmsu_idle_prepare(),
have been merged into a single function called
armada_370_xp_pmsu_idle_enter() by the commit "bbb92284b6c8 ARM:
mvebu: slightly refactor/rename PMSU idle related functions".

But for CPU Idle the prepare function will be common to all the mvebu
SoC that use a psmu whereas the suspend function will be specific to
each SoC. Keeping the prepare function separate will help to reduce
code duplication while new SoC support will be added.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: Sort the headers of pmsu.c in alphabetic order

Sorting the headers in alphabetic order will help to reduce the
conflict when adding new headers later.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: Add a common function for the boot address work around

On some of the mvebu SoC and due to internal BootROM issue, the CPU
initial jump code should be placed in the SRAM memory of the SoC. In
order to achieve this, we have to unmap the BootROM and at some
specific location where the BootROM was placed, create a specific MBus
window for the SRAM. This SRAM is initialized with a few instructions
of code that allows to jump to the real secondary CPU boot
address. The SRAM used is the Crypto engine one.

This work around is currently needed for booting SMP on Armada 375 Z1
and will be needed for cpuidle support on Armada 370. Instead of
duplicating the same code, this commit introduces a common function to
handle it: mvebu_setup_boot_addr_wa().

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: Use the common function for Armada 375 SMP workaround

Use the common function mvebu_setup_boot_addr_wa() introduced in the
commit ARM: mvebu: Add a common function for the boot address work
around" "instead of the dedicated version for Armada 375.

This commit also moves the WA in the system-controller module. Indeed
the workaround on 375 is really related to setting the boot address
which is done by the system controller.

In bonus we don't use anymore an harcoded value to access the register
storing the boot address.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: Rename the armada_370_xp into mvebu_v7 in pmsu.c file

Actually most of the function related to the PMSU are not specific to
the Armada 370 or Armada XP SoCs, but can also be used for most of the
other mvebu ARMv7 SoCs.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: Make the CPU idle initialization more generic

In order to support more mvebu SoCs, this patch use an initialization
specific function associated to each SoCs which support CPU Idle.

Then each SoC will have his own set of check and of data
configuration.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: Use a local variable to store the resume address

The resume address used by the cpu idle code will not always be the
same. Using a local variable to store the resume address allows to
keep the same function for the pm notifier but with a different
address. This address will be set during the initialization.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: Make the snoop disable optional in mvebu_v7_pmsu_idle_prepare

On some mvebu v7 SoC (the ones which don't use PJ4B core) there is no
such feature. So add a parameter in mvebu_v7_pmsu_idle_prepare function
to make its use optional.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: Export the SCU address

The SCU address will be needed in other files than the board file, for
example in pmsu.c. So this patch adds a function allowing to get the
SCU address.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: dts: Add CA9 MPcore SoC Controller node

The CA9 MPcore SoC Control block allows to do some configuration that
the SoC could use for a specific use case. In most cases the defaults
case is enough. However there is few exception: for cpuidle we need to
use the CA9 MPcore Reset Control register.

The documentation is also updated in the same time.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: devicetree@vger.kernel.org
cpuidle: mvebu: Rename the driver from armada-370-xp to mvebu-v7

Actually this driver will be able to manage the cpuidle for more SoCs
that Armada 370 ad XP. It will support Armada 38x and potentially
Armada 375. This patch change the names accordingly to this behavior.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
cpuidle: mvebu: Move the description of the cpuidle states in the platform part

In order to prepare the add of new SoCs supports for this cpuidle
driver, this patch moves the description of the state in the platform
part. Indeed the number of the cpuidle state, and the value of the
flag used will vary depending of the SoC.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: Add CPU idle support for Armada 370

Unlike the Armada XP the Armada 370 always power done the L2 cache, so
it have only 2 cpuidle states.

On Armada 370, there is "a slow exit process from the deep idle state
due to heavy L1/L2 cache cleanup operations performed by the BootROM
software" (cf errata GL-BootROM-10). To avoid this, we replace the
restart code of the BootROM by a simple jump to the boot address. Then
the code located at this boot address will take care of the
initialization.

For this purpose, we use the common function mvebu_boot_addr_wa()
introduced in the commit "ARM: mvebu: Add a common function for the
boot address work around".

Thanks to the previous patches, adding the support for this new SoCs
required only the modification of the architecture specific part.

The message in case of failure to suspend the system was switched from
warn to debug. Indeed due to the "slow exit process from the deep idle
state" in Armada 370, this situation happens quite often. Using the
_debug version avoids spamming the kernel logs, but still allows to
enable it if needed.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: Add CPU idle support for Armada 38x

Unlike the Armada XP and the Armada 370, this SoC uses a Cortex A9
core. Beside this, the main difference for the cpu idle is the way to
handle the L2 cache and the use of SCU.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: defconfig: Enable CPU Idle support in mvebu_v7_defconfig

mvebu SoCs such as Armada 370, Armada XP or Armada 38x now support CPU
Idle so let's add it in the default configuration.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>