rpmsg: omx: copy_from_user() errors should return -EFAULT

Change-Id: Ib4a2d92dd3b8afa18e60019871cfea2e6b446a4d
Signed-off-by: David Schleef <ds@ti.com>
remoteproc: fix obsolete comment about memory_maps

memory_maps in remoteproc platform data has been replaced
with memory_pool, but the comment still remained. It has
been cleaned up.

Change-Id: Iae78c0b8e8d4caccce2fc0248b89a9d18f8d7cca
Signed-off-by: David Schleef <ds@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
rpmsg: omx: return ENXIO in rpmsg_omx_write

The error code, ENXIO is used in rpmsg_omx driver to indicate
a terminal error on the remote processor side. This status is
maintained during the recovery of the remote processor, while
the cdev gets reinitialized/recreated.

The rpmsg_omx's write file operation is currently not returning
this error. This has been added now to have it behave in the
same way as the read file operation.

Change-Id: I61d6e6c07aa39208d913da622ed32d809c51d409
Signed-off-by: Vidhoon Viswanathan <vidhoon@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
remoteproc: add a notify event for firmware preload

Added a new rproc event, RPROC_PRELOAD, to send a notification
about commencement of loading of a image into remoteproc's
memory. This event will currently be used for bumping up the
remoteproc frequency to optimize the overall boot time of the
remote processor.

Change-Id: I7e36e54fe938b3242b9e87fd33d6e190a1233083
Signed-off-by: Chandra Sekhar.Anagani <chandu@ti.com>
omap: rpmsg: bump to max freq while booting remote processor

Reduce the remote processor booting time by bumping to the max
frequency. This is achieved by putting in constraints before
the loading of the remote processor. The latter is known through
the RPROC_PRELOAD notification.

Once the remote processor has reached a certain point, it would
send a message, RP_MSG_BOOTINIT_DONE via mailbox to notify the
host that the remote processor has completed the basic boot and
initization. The constraints are released upon receipt of this
message. They are also released in case of an error during
loading.

NOTE: The current implementation used tput api for ipu since
freq scale api is not supported directly yet.

Change-Id: I1fe936087f00872756c7b532ee58d923e695ff28
Signed-off-by: Miguel Vadillo <vadillo@ti.com>
Signed-off-by: Fernando Guzman Lugo <fernando.lugo@ti.com>
Signed-off-by: Subramaniam C.A <subramaniam.ca@ti.com>
Signed-off-by: Chandra Sekhar.Anagani <chandu@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
OMAPDSS: DISPC: fix pclk divisor limits

According to TRM, minimal pixel clock divisor value can be 1.
Fix corresponding checks, as high resolution panels use undivided
pixel clock frequency.

Also certain scaler unit constraint must be met: in case DISPC_CLK
and pixel clock frequencies are equal, set IPC to work on rising edge.

Change-Id: Iabeac2ad81f6909213cb81f4e16b1d0762369b53
Signed-off-by: Sergiy Kibrik <sergiy.kibrik@globallogic.com>
Signed-off-by: Lajos Molnar <lajos@ti.com>
Signed-off-by: Dima Svetlov <svetlov@ti.com>
Input: Add driver for Cypress touchpanels

Supports CY8CTMA398 & CY8CTMA884

Change-Id: Ifcdba380e3a8712716054dd6c5d807ebb2c1beb6
Signed-off-by: Peter Nordström <nordstrom@ti.com>
Signed-off-by: Lajos Molnar <lajos@ti.com>
Signed-off-by: Dima Svetlov <svetlov@ti.com>
OMAPDSS: MFlag thresholds settings

As per the simultaion team suggestion, the below thesholds are set:
HT = fifosize * 5/8;
LT = fifosize * 4/8;

Change-Id: Ieef7d8a090e38ce717729fe30f60f46c6dfd6ddd
Signed-off-by: Sunita Nadampalli <sunitan@ti.com>
Signed-off-by: Lajos Molnar <lajos@ti.com>
Signed-off-by: Dima Svetlov <svetlov@ti.com>
Revert "OMAPDSS: Increase PLL1_CLK1 frequency for correct work with large panels"

This reverts commit 1fe611b1c2eea594ed3738d50bfb37a701d2632c.

Change-Id: I444e0e09a99ce5f495ffc298d388678e0e07cda4
Signed-off-by: Dima Svetlov <svetlov@ti.com>
ION: Added support for getting ion phys without client

In order to dereference the ion_handles passed from user side
to kernel, there should be support for api without client identity.
This patch adds this support.

Change-Id: I95d0d460c9e0ad202d14e7620b82e1fa9d48f746
Signed-off-by: Sunita Nadampalli <sunitan@ti.com>
Signed-off-by: Lajos Molnar <lajos@ti.com>
Signed-off-by: Dima Svetlov <svetlov@ti.com>
OMAPDSS: drop small YUV encoded frames on OMAP44xx

OMAP44xx has hardware limitation: in stall mode, when the frame pixel size
is less than output SyncFifo depth(16), DISPC hangs without sending any data.
Simple workaround is to drop such frame, as cases when YUV frames of this size
are very rare.

Change-Id: I31dc262b07a52b66209c093f136ad2bac66f9439
Signed-off-by: Sergiy Kibrik <sergiy.kibrik@globallogic.com>
OMAP4: PM: IVA AUTO RET relaxed workaround in idle path

AUTO RET for IVA VDD Cannot be permanently enabled during OFF mode due to
potential race between IVA VDD entering RET and start of Device OFF mode.

It is mandatory to have AUTO RET for IVA VDD exlusive with Devide OFF mode.
In order to avoid lockup in OFF mode sequence, system must ensure IVA
voltage domain transitions straight from stable ON to OFF.

In addition, management of IVA VDD SmartReflex sensor at exit of idle path
may introduce a misalignment between IVA Voltage Controller state and IVA
PRCM voltage FSM based on following identified scenario:

IVA Voltage Controller is woken-up due to SmartReflex management while
IVA PRCM voltage FSM stays in RET in absence of any IVA module wake-up event
(which is not systematic in idle path as opposed to MPU and CORE VDDs being
necessarily woken up with MPU and CORE PDs).

WA involves:
Ensure stable ON-OFF transition for IVA voltage domain during OFF mode sequence.
Ensure VCON and PRCM FSM are kept aligned due to IVA SR handling in idle path.
1) AUTO RET for IVA VDD is enabled entering in idle path, disabled exiting idle
   path and IVA VDD is always woken-up with a SW dummy wakeup.
2) OFF mode is enabled only in Suspend path.
3) AUTO RET for IVA VDD remains disabled in Suspend path (before OFF mode).

REVISIT: Update the patch once proper Errata is out for 44xx.

Benefits:
1) This patch ensures it is possible to gate SYS_CLK during OS-Idle LCD OFF
when all domains are idled, saving up to 2mA at VBAT from external clock buffer.

2) IVA voltage domain is now allowed to scale to Retention during idle which
reduces power consumption on all types of use case allowing extensive use of
idle path (e.g.: Home screen, Page reading). Effects are especially visible
if system uses Smart-Reflex Class 1.5 compared to Class 3 considering the
increased difference of voltage from converged Voltage SR vs Retention voltage.

TODO: quantify the actual savings from IVA-RET with further measurements.

Change-Id: I01f0431f7556f0baf0b5b6b42092cd11c2442f00
Signed-off-by: Cedric Vamour <c-vamour@ti.com>