Refine messages regarding AMD FCH flash protections.

Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

git-svn-id: svn://flashrom.org/flashrom/trunk@1829 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Add support for AMD Bolton chipset.

SPI controller on the bolton chipset uses the same 3-bit speed
settings as Yangtze, but is otherwise the same as the Hudson chips.
Note that the Bolton RRG doesn't specify a speed setting for the bit
setting of 0b111, so I'm assuming that it's the same setting as
Yangtze.

Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

git-svn-id: svn://flashrom.org/flashrom/trunk@1830 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1