cfg80211: change regulatory rules for Indonesia

Change regulatory rules for Indonesia as per the
directive from regulatory compliance team.

Change-Id: If25a3100a94492191b322310406ae9047bd6f4a2
CRs-Fixed: 637303
Signed-off-by: Mihir Shete <smihir@codeaurora.org>
mmc: core: Fix clock frequency transitions during invalid states

eMMC and SD card specifications restrict the usage of a class of
commands while commands in other class are in progress. For example,
during erase operations the SD/eMMC spec. allows only CMD35, CMD36,
CMD38. If clock scaling is enabled and decide to scale up the clocks
it may be possible that CMD19/21 tuning commands are sent in between
erase commands, which is illegal as per specification.

Fix such illegal transactions to the card and also make clock scaling
statistics accountable only for read/write commands instead of time
consuming commands, like CMD38 erase, where transactions are independent
of bus frequency.

Change-Id: Iffba175787837e7f95bde8970f19d0f0f9d7d67d
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
wcnss: Unregister subsys notifier

Unregister subsys notifier for WCNSS on reaching
maximum number of retries.

Change-Id: I665398ec46b1bb3252dbbff58201c947f262bff3
CRs-Fixed: 655314
Signed-off-by: Pradeep Kumar Goudagunta <gpradeep@codeaurora.org>
mmc: core: fix block request queue hang during data crc errors

When data CRC errors occur during write transactions, mmc
block layer queries the card for successful writes. If the card
reports bytes requested as bytes successfully written, the mmc
block layer will end the request with blk_end_request(). If there
is a following async request pending for execution, the request
is thrown away while handling CRC errors leading to hang in
request queue. The hang is visible when user issues a sync()
system call.

The sequence of events are as follows -

mmcqd -> fetch a request -> send it to host driver -> fetch another
request -> wait for previous request to complete -> previous request
is in error -> skip sending current request to host driver and
do error handling for previous request in error.

During the last step, after error handling is completed the mmc
block layer does not requeue the current request which is skipped
and hence the request is infinitely stuck in the driver.

Change-Id: I9528fbe3ccb5b723fcd0793f86cca43906c4c29c
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
mmc: card: quirk: disable cache for Kingstone card

This change prevents enabling cache during card init for specific
Kingstone card.
This change is workaround the problem of long timeouts for cache
operations.

CRs-Fixed: 625480
Change-Id: I6be53a408c7d6422556585d4ea2f9b1c487563e0
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
qseecom: Replace kzalloc with ion_alloc

Allocate memory to common lib through kzalloc issues no page error due to
higher order memory request. So allocate the memory from the heap specially
dedicated to QSEECOM.

Change-Id: Ice4a609d6791ce5adc84b9882231def31674f461
Signed-off-by: AnilKumar Chimata <anilc@codeaurora.org>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
qseecom: Fix failure to load cmnlib image

Set the physical address field of load_req data struct
correctly using the right ion_phys API.Without this,
secure domain is not able to address/dereference memory
where cmnlib image resides.

Change-Id: I9f75e78227e4eee89fff9ad8b19701ff08e5d90a
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
qseecom: Check the return value of "ion_phys"

Check for return value of "ion_phys" and handle
the error case appropriately.

Change-Id: Ib4f24af24de2b2553ed91479f46b2f79e0be0446
Signed-off-by: Hariprasad Dhalinarasimha <hnamgund@codeaurora.org>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
qseecom: register bus bandwidth mode when loading app

when there are multiple running qseecom clients, ce clock may be disabled
by one client while TZ is still loading another client's app, which will
lead to load app failure. So, we make a change to register bus bandwidth
mode before loading app and avoid to disable clock when current bandwidth
mode is not INACTIVE.

Change-Id: I1727f6fc038baf95da39089e1f0faefe42f3d40c
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
qseecom: update cumulative_mode and timer properly

qseecom.cumulative_mode is used to track the cummulative bus request
mode from all concurrent running clients. It is registered before
send_cmd operation, but is not un-registered after it is complete.
This may cause the bus bandwidth is restored to a wrong mode after
resuming from sleep.Thus, we make change to update it accordingly.
qseecom.current_mode is also updated in suspend/resume function to
ensure timer can scale down bus bw after resume when cumulative_mode
is non-zero. Besides, timer operation is optimized in case there are
multiple unserialized concurrent users of the same timer.

Change-Id: I06043d2b88a47e24da03460fe1ae26a94cb6a608
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
msm: vidc: ensure venus clocks are enabled while release buffer

While interframe clock gating, venus clock are gated ON and
OFF based on firmware response. It may happen that venus
clocks are disabled while iommu driver unmaps output buffers.
This may lead to unclocked memory access.
Venus clocks should be enabled while releasing output buffers.

Change-Id: Ib7a04c2d3600ae91a229730e2caffbff9c8353ca
CRs-Fixed: 645657
Signed-off-by: Vikash Garodia <vgarodia@codeaurora.org>
msm: mdss: Add support for sending panel off commands in LP mode

Add support to send panel Off commands for video mode during LP
mode. This is needed to support few video mode panels which have
BLLP power mode set to HS and it is not possible to send Off
commands when pixel data is active. Hence, make changes to send
panel Off commands for such panels in LP mode after TG is
turned off.

Change-Id: I1c9f3fd1e9e052b5254cfdcf58cd974dfbe3dc8e
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
msm: kgsl: Enable protected register mode for A3XX

Turn on protected register mode for the A3XX GPU family and add 0x63
(RBBM_INT_0_MASK) to the list of protected registers.

Conflicts:

        drivers/gpu/msm/adreno.h
        drivers/gpu/msm/adreno_a3xx.c

Change-Id: Ic0dedbad10ebfa6eb6d3d815b5aa9b6b6f0e8e35
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Digish Pandya <digishp@codeaurora.org>
msm: kgsl: Protect CP_STATE_DEBUG_INDEX

Put CP_STATE_DEBUG_INDEX and CP_STATE_DEBUG_DATA under protection
to keep it from being written from an IB1. Doing so however opens
up a subtle "feature" in the microcode: memory read opcodes turn off
protected mode in the microcode to do the read and then turns it
back on regardless of the initial state. This is a problem if the
memory read happens while protected mode is turned off and then we
try to access a protected register which then complains and goes boom.

To account for this irregularity explicitly turn back off protected
mode in all the places where we know this will be a problem.

Change-Id: Ic0dedbad1397ca9b80132241ac006560a615e042
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Digish Pandya <digishp@codeaurora.org>
Merge "cfg80211: change regulatory rules for Indonesia"
Merge "mmc: core: Fix clock frequency transitions during invalid states"
Merge "mmc: core: fix block request queue hang during data crc errors"
msm: mdss: Turn off backlight while power off

Turn off the backlight while shut down panel as it
could show white flicker depending on the panel.

Change-Id: Ic5d4e97e70c87e5b6e956e27a766136610d6f345
Signed-off-by: Shuo Yan <shuoy@codeaurora.org>
Merge "mmc: card: quirk: disable cache for Kingstone card"
msm: mdss: protect command mode BW votes by tracking HW/SW states

Track two states where the BW is needed for the command mode panels
and prevent the BW vote to be released during any of those two states:
1. SW Commit State: This state is the time when the SW has requested
a BW vote, and it will be processing it; it starts at the beginning of
Commit and finish once the kickoff is issued.
2. HW MDP State: This state is the time when the HW is busy
doing the actual transaction, so bandwidth must be kept until
HW finishes; it starts at the beginning of the kickoff and finishes
once the ping pong done interrupt is received.

Change-Id: I2e56128be3ab25a1b065692ae76387a3cd383df3
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>