[C++11] Replace some comparisons with 'nullptr' with simple boolean checks to reduce verbosity.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205829 91177308-0d34-0410-b5e6-96231b3b80d8
[C++11] Make use of 'nullptr' in TableGen library.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205830 91177308-0d34-0410-b5e6-96231b3b80d8
[C++11] More 'nullptr' conversion or in some cases just using a boolean check instead of comparing to nullptr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205831 91177308-0d34-0410-b5e6-96231b3b80d8
ARM MC: sort source files in CMakeLists

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205832 91177308-0d34-0410-b5e6-96231b3b80d8
ARM MC: 80 column

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Object: add type names for ARM/COFF relocations

Add type name mappings for the ARM COFF relocations.  This allows for objdump to
provide a more useful description of relocations in disassembly inline form.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205834 91177308-0d34-0410-b5e6-96231b3b80d8
ARM64: add pattern for <1 x i64> custom not node.

This should fix PR19367.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205835 91177308-0d34-0410-b5e6-96231b3b80d8
ARM64: scalarize v1i64 mul operation

This is the second part of fixing PR19367.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205836 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Match not instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205837 91177308-0d34-0410-b5e6-96231b3b80d8
Delinearize: Extend informationin -analyze output

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205838 91177308-0d34-0410-b5e6-96231b3b80d8
YAMLIO: Encode ambiguous hex strings explicitly

YAMLIO would turn a BinaryRef into the string 0000000004000000.
However, the leading zero causes parsers to interpret it as being an
octal number instead of a hexadecimal one.

Instead, escape such strings as needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205839 91177308-0d34-0410-b5e6-96231b3b80d8
Re-commit: [mips] abs.[ds], and neg.[ds] should be allowed regardless of -enable-no-nans-fp-math

Summary:
They behave in accordance with the Has2008 and ABS2008 configuration bits of the processor which are used to select between the 1985 and 2008 versions of IEEE 754. In 1985 mode, these instructions are arithmetic (i.e. they raise invalid operation exceptions when given NaN), in 2008 mode they are non-arithmetic (i.e. they are copies).

nmadd.[ds], and nmsub.[ds] are still subject to -enable-no-nans-fp-math because the ISA spec does not explicitly state that they obey Has2008 and ABS2008.

Fixed the issue with the previous version of this patch (r205628). A pre-existing 'let Predicate =' statement was removing some predicates that were necessary for FP64 to behave correctly.

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3274



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205844 91177308-0d34-0410-b5e6-96231b3b80d8
Add support for building LLVM on FreeBSD 9.2

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205847 91177308-0d34-0410-b5e6-96231b3b80d8
AVX-512: insert element to mask vector; store i1 data

Implemented INSERT_VECTOR_ELT operation for v16i1 and v8i1 vectors;
Implemented "store" for i1 type


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205850 91177308-0d34-0410-b5e6-96231b3b80d8
SLPVectorizer: Only vectorize intrinsics whose operands are widened equally

The vectorizer only knows how to vectorize intrinics by widening all operands by
the same factor.

Patch by Tyler Nowicki!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205855 91177308-0d34-0410-b5e6-96231b3b80d8
Revert "YAMLIO: Encode ambiguous hex strings explicitly"

This reverts commit r205839.

It broke several tests in lld.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205857 91177308-0d34-0410-b5e6-96231b3b80d8
[ARM64] Register-offset loads and stores with the 'option' field equal to 00x or 10x are undefined.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205858 91177308-0d34-0410-b5e6-96231b3b80d8
[ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB instructions is unallocated if shift > 4.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205859 91177308-0d34-0410-b5e6-96231b3b80d8
[ARM64] STRHro and STRBro were not being decoded at all.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205860 91177308-0d34-0410-b5e6-96231b3b80d8
[ARM64] Correctly alias LSL to UXTW for 32bit instruction variants, rather than UXTX

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205861 91177308-0d34-0410-b5e6-96231b3b80d8