sunxi: dram: Fix autorefresh timing setup

This patch unifies sun4i and sun[5,7]i autorefresh setup functions
and adds proper tRFC calculation.

tRFC (REF command to ACT time) depends on DDR type and chip density.

On sun4i there were two steps, 127.5ns for <=1Gb density and 327.5ns
for the rest. This fits DDR2 specification for 1Gb and 4Gb chips
and shouldn't be a problems with DDR3 chips <8Gb either, but it will
waste some performance.

On sun[5,7]i however, tRFC was hardcoded to 131 clock cycles, which
seems to come from 4Gb DDR2 chips at 400MHz (327.5ns * 400MHz = 131).
For 4Gb DDR3 chips, like those on cubieboard2 and cubietruck, this
means the memory frequency was limited to ~435MHz if one doesn't want
to fall below the minimum specified tRFC for these chips.

Signed-off-by: Jens Kuske <jenskuske@gmail.com>
ARM: sunxi: Compile DRAM related code only when building SPL

The code of DRAM initialization is only of interest when building the SPL. Move
it to the CONFIG_SPL-only list of files to build.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi: Add basic A31 support

Add a new sun6i machine that doesn't do much for now.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi: Setup the A31 UART0 muxing

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi: Add sun6i clock controller structure

The A31 has a new clock controller of its own. Add the structure representing
this controller register layout.

HdG: Move sun4i ccm register definitions to clock-sun4i.h and put the new
sun6i ccm register definitions in clock-sun6i.h

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sun6i: Setup the UART0 clocks

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi: Enable pll6 by default on all models

So that we can use it as a clocksource for modules, ie for mmc. This
allows discoupling the actual mmc clock rate we get from the ram speed,
and will lead to getting exact clockspeeds for mmc rather then something
approximately right.

As an added bonus this makes things easier on sun6i since pll5 cannot be
used as a module source at all there.

This has been tested on sun4i, sun5i and sun7i.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi-mmc: Make mmc mod clk div pll clk freq independent

Change how we calculate the mod clk div so that it will work for a pll clk
of 600 or 1200 too.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi-mmc: Use pll6 as clock source

This discouples the actual mmc clock rate we get from the ram speed,
which leads to getting exact clockspeeds for mmc rather then something
approximately right.

As an added bonus this makes things easier on sun6i since pll5 cannot be
used as a module source at all there.

This has been tested on sun4i, sun5i and sun7i.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi-mmc: Simplify data_buf1_sz calculations

Since SDXC_DES_BUFFER_MAX_LEN is always a power of 2,
"(SDXC_DES_BUFFER_MAX_LEN - 1) & SDXC_DES_BUFFER_MAX_LEN" is just a really
complicated way of writing 0.

Since writing 0 to data_buf1_sz means transfer SDXC_DES_BUFFER_MAX_LEN bytes,
there is no need to set remain to SDXC_DES_BUFFER_MAX_LEN when it is 0.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi-mmc: Add mmc support for sun6i / A31

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sun6i: Fix clock_twi_onoff for sun6i

Note this is something I noticed while working on the clock stuff for the
mmc support. Likely more work is needed to get twi to work on sun6i, this
is just a first step.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sun6i: sun6i can have upto 2G RAM

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sun6i: Add initial clock setup for SPL

With this patch and built with SPL,NO_AXP options added, it is possible
to build a non-functional SPL for the A31, which will properly load and
print its banner on the serial console:

U-Boot SPL 2014.04-rc2-01254-g7e81174-dirty (Mar 28 2014 - 21:09:16)
Board: Colombus
sun6i SPL support is not yet complete

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi: Split clock code into common, sun4i and sun6i code

Rather then having effectively 2 copies of a function through
 #ifdef CONFIG_SUN6I ... #else ... #endif, really make 2 copies of the
function in 2 separate C-files, this is much easier to read and maintain.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sun6i: Add base address for the new controllers in A31

A31 has several new and changed memory address. This patch adds them.

Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sun6i: Add support for the new power control module found on the A31

To setup clocks and control voltages.

HdG: Rename the files from the somewhat generic pmu name to prcm.{c,h}
HdG: Make the prcm code only deal with the prcm, remove axp221 bits

Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sun6i: Properly setup the PLL LDO in clock_init_safe

This fixes me being unable to use PLL6 as clock-source for the mmc controller.
Unfortunately the DRAM controller situation is a mess. Someone will need
to put a lot of time into getting DRAM going before we can do SPL on sun6i.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sun6i: Add support for gpio bank L

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sun6i: Define P2WI GPIO pins

P2WI needs 2 pins configured from the GPIO pins. This adds defines to be
used for that.

Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>