quark_x10xx: fix IO r/w operations with paging enabled

Paging checking and disabling wasn't present for IO r/w,
so the commands were successful only when paging wasn't
enabled (e.g. EFI boot phase).

Change-Id: I41366c0fadff3ea1eb8a153291f20a46cd9ddec1
Signed-off-by: Ivan De Cesaris <ivan.de.cesaris@intel.com>
Reviewed-on: http://openocd.zylin.com/2118
Tested-by: jenkins
Reviewed-by: Peter Stuge <peter@stuge.se>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
nrf51: remove dereference of null pointer

found by clang 3.4.

Change-Id: Id499b546f65acd7a719498bc97e33b21d1ba565a
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/2119
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Andrey Smirnov <andrew.smirnov@gmail.com>
The openocd-0.8.0 release

Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Restore normal development cycle

Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Add support for Gumstix AeroCore device

The Gumstix AeroCore board [1] contains a STM32F427 microcontroller.
Schematics for this board will also be made available [2].
The JTAG interface for this chip can be accessed via a USB connection
provided by an FTDI chip (0403:6011).

[1] https://store.gumstix.com/index.php/products/585/
[2] https://pubs.gumstix.com/boards/AEROCORE

Change-Id: I0bf3bb525f51528bedd807b1f7210b09ef2e1015
Signed-off-by: Ash Charles <ashcharles@gmail.com>
Reviewed-on: http://openocd.zylin.com/2117
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Fix some C99 format specifiers

As exposed by arm-none-eabi build, fix the wrong modifiers.

Change-Id: Ia6ce7c5c1d40e95059525c3e5d81b752df2fea7c
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2122
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
armv7a: fix typo in cache_config help text

Change-Id: I48cb83bf56b2f6841c3add68ed94b9f92037357d
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/2114
Tested-by: jenkins
generalplus: Add configuration file for General Plus GP326XXXA series

Add configuration file for General Plus GP326XXXA series. Tested on
GP326833A on GPC-1737B board.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Change-Id: I1ad0e22598b01317bbc823870a7a262e9192c595
Reviewed-on: http://openocd.zylin.com/2058
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
doc: document [start end] parameters of "profile" command

Change-Id: I56561b08304e5b854a67b06ab6b9cee7a24919b2
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2115
Tested-by: jenkins
svf: Fix debug and error messages that print hex buffer

Added SVF_BUF_LOG macro to properly print the hex buffer of parsed
string for SIR, SDR, TDI, TDO and MASK. The original debug and error
logs with respect to printing real values were misleading and also
had endianess issues. All the bits are printed now instead of just
u32 values.

Change-Id: Ie89902403bdb61ff458418446c2ca1253ea2a63f
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Reviewed-on: http://openocd.zylin.com/1964
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
ftdi: Optimize GPIO toggling

Only send the new I/O state for the bytes that changed.

Change-Id: I930edc9518e6019331e68e4756acc5e92dda25a4
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/1999
Tested-by: jenkins
Reviewed-by: Jens Bauer <jens@gpio.dk>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
README.OSX: recommend XCode 5 as that's the current version

Using current "Command Line Tools" with XCode 4 is known to provoke
issues (the build "hangs"), see e.g.

http://stackoverflow.com/questions/18667916/xcrun-lipo-freezes-with-os-x-mavericks-and-xcode-4-x

This fixes https://sourceforge.net/p/openocd/tickets/70/ .

Change-Id: I511b347b9388e0e3f1d136b566915021c4b5fbde
Reported-by: n321203 <n321203@users.sf.net>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2128
Reviewed-by: Xiaofan <xiaofanc@gmail.com>
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Update to the current Jim Tcl

This is a post-release version but hopefully some fixes that went in
are worth it; also the changes here make OpenOCD compatible with stock
0.75 version if a distro maintainer decides to use it.

Change-Id: I7ad1814c7c4868198475cdca4750c3d0ee4f5f8b
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2121
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
mips32: optimized cache code for pracc access

Follows the the same rules of optimization used by all pracc functions.
Solves some bugs in previous code and adds support for write through caches.

Change-Id: If88c6738ca8c8197f327f22b766120a24f71b567
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1557
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
mips: load code in buffer mode

Currently the functions mips32_checksum_memory() and mips32_blank_check_memory()
load the code word by word.
The bug in cache code is a good reason for doing so.
If there is no other reason we can load the code as a buffer to save time.
mips_m4k_write_memory() expect a buffer in target endianness, this is done by
target_buffer_set_u32_array().
Cleaned up exit code.
Tested on ar7241 big endian and pic32mx little endian with verify_image.
Flash erase check only tested in pic32mx.

Change-Id: Ib63ed98732b2e23b058e7349a0a57934b7604905
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1562
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
mips: load fast data transfer handler code with mips32_pracc_write_mem()

Currently the code is loaded calling mips32_pracc_write_mem_generic().
Cache synchronization is not performed.
If configured as write back cache there is no chance to execute the
handler. If configured as write through cache and the cache
lines written to are not cache resident (I-side cache miss) may work.
The patch makes possible to execute the handler in a cached active
memory segment (mainly from KSEG0), but nothing else. The data
is still loaded without performing cache synchronization, code loaded
may not be executable.
Performance may not be faster. At start, for example, the code resides in
main memory, not in cache, and the core must transfer code from
memory. We can really modify the code to force a wait for the first
transfer like we do with start and end addresses, making sure the code
is cache resident for the rest of the queued transfers.
This can also may happen if we execute code (greater than the I cache size)
and the handler code is evicted from the cache.
Code tested on ar7241.

Change-Id: Iffdb4dae108b872fef0e7bacc5ea99649cdc1630
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1564
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
mips: use cp0 DeSave to cache $15 / t7

Near all pracc functions store $15 in DeSave and
restore it when exiting.
There is no need to save it, if mips32_pracc_read_regs()
save this register in Desave when entering debug mode.
mips32_pracc_write_regs() needs to update it when
exiting debug mode.
Other pracc functions must not modify DeSave.
The jump code in the fastdata transfer function needs also
some little modifications.
Remark:
Like in current code the user can read/modify $15
with the cp0 31 commands.

Change-Id: I5b7dfc1b6169da846f5d2dd3ad4209a9da2c3fad
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1565
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
mips32: cleanups in legacy pracc code
This is the first patch intended to make a more precise pracc check
when running in legacy mode (code executed by mips32_pracc_exec()).
It only makes some cleanups, mostly due to unnecessary code.
With the last cache optimizations for processor access (pa for short)
all the pracc functions generate the code following some rules that
make pa more easily to check:
	There are no load instructions from dmseg. All the read pas are
	instruction fetches. PARAM_IN related stuff is not needed.
	Registers are restored either from COP0 DeSave or from ejtag
	info fields. PRACC_STACK related stuff is not needed any more.
	The code starts execution at PRACC_TEXT and there are no branch or jump
	instruction in the code, apart from the last jump to PRACC_TEXT.
	The fetch address is ever known.
	For every store instruction to dmseg the function code sets
	the address of the write/store pa.
	The address of every store pa is known.
Current code ends execution when reading a second pass through PRACC_TEXT.
This approach has same inconveniences:
	If the code starts in the delay slot of a jump it makes a jump
	to PRACC_TEXT after executing the first instruction. A second pass
	through PRACC_TEXt is read and the function exits without any warning.
	This seems to occur sometimes when a 24kc core is halted in the delay
	slot of a branch.
	If a debug mode exception is triggered during the execution of a
	function the core restarts execution at PRACC_TEXT. Again the function
	exits without any warning.
	If for whatever reason the core starts fetching  at an unexpected
	address the code now sends a jump instruction to PRACC_TEXT, but due
	to the delay slot the core continues fetching at whatever address + 4
	and a second jump instruction will be send for execution. The result
	of a jump instruction in the delay slot of another jump is
	UNPREDICTABLE. It may work as expected (ar7241), or let the core in
	the delay slot of a jump to PRACC_TEXT for example. This means the
	function called next may also fail (pic32mx).

Change-Id: I9516a5146ee9c8c694d741331edc7daec9bde4e3
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1825
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
mips32: new code for pracc exec

This is only the basic code proposed for mips32_pracc_exec() function.
It checks every pracc address against the expected address when
reading (instruction fetch).
The code expects to start at PRACC_TEXT and any subsequent read address
is obtained by adding 4 to the previous one.
After shifting out all the instructions the code executes a final check.
It checks now for the first pass trough PRACC_TEXT and shift out
only NOP instructions.
A mips core does not need an additional NOP and after the first check
it exits if there is no store access pending.
After shifting out one NOP the core must be reading at pracc text or the
code exits with error.
The code continues shifting out NOPs until all store accesses have
been performed.
After shifting out 10 NOPs it exits with error.
No assumption is made about the number of store instruction shifted out or
the ordering of the store accesses. It only checks that the number of
store accesses is the same as the number of store instructions at dmseg
after execution.
mips32_pracc_read_ctrl_addr() and mips32_pracc_finish() are added to
simpify a bit the code. Fields pa_ctrl and pa_addr are added
in ejtag_info for storing values of pracc control and address.

Change-Id: If6322d5c8cbeadcd4acd3972c0f72c8490f53c34
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1827
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
kinetis: Revise CPU un-securing code

Old version of the code had several problems, among them are:
 * Located in a generic ADI source file instead of some Kinetis
   specific location
 * Incorrect MCU detection code that would read generic ARM ID
   registers
 * Presence of SRST line was mandatory
 * There didn't seem to be any place where after SRST line assertion
   it would be de-asserted.
 * Reset was asserted after waiting for "Flash Controller Ready" bit
   to be set, which contradicts official programming guide AN4835
 * Mass erase algorithm implemented by that code was very strange:
   ** After mass erase was initiated instead of just polling for the
      state of "Mass Erase Acknowledged" bit the code would repeatedly
      initiate mass erase AND poll the state of the "Mass Erase
      Acknowledged"
   ** Instead of just polling for the state of "Flash Mass Erase in
      Progress"(bit 0 in Control register) to wait for the end of the
      mass erase operation the code would: write 0 to Control
      register, read out Status register ignoring the result and then
      read Control register again and see if it is zero.
 * dap_syssec_kinetis_mdmap assumed that previously selected(before
   it was called) AP was 0.

This commit moves all of the code to kinetis flash driver and
introduces three new commands:

o "kinetis mdm check_security" -- the intent of that function is to be used as
  'examine-end' hook for any Kinetis target that has that kind of
  JTAG/SWD security mechanism.

o "kinetis mdm mass_erase""  -- This function removes secure status from
  MCU be performing special version of flash mass erase.

o "kinetis mdm test_securing" -- Function that allows to test securing
  fucntionality. All it does is erase the page with flash security settings thus
  making MCU 'secured'.

New version of the code implements the algorithms specified in AN4835
"Production Flash Programming Best Practices for Kinetis K-
and L-series MCUs", specifically sections 4.1.1 and 4.2.1.
It also adds KL26 MCU to the list of devices for which this security
check is performed. Implementing that algorithm also allowed to simplify
mass command in kinetis driver, since we no longer need to write security
bytes. The result that the old version of mass erase code can now be
acheived using 'kinetis mdm mass_erase'

Tested on accidentally locked FRDM-KL26Z with KL26 Kinetis MCU.

Change-Id: Ic085195edfd963dda9d3d4d8acd1e40cc366b16b
Signed-off-by: Andrey Smrinov <andrew.smirnov@gmail.com>
Reviewed-on: http://openocd.zylin.com/2034
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>