cleanup
cleanup
src/ add ccd_vita25K.vhd
src/ clocks.vhd set clk for ccd 310Mhz
src/
src/ add prj_cfg.vhd
ucf/
ucf/ fix bug pin location
src/ add deser_lvds_ccd.vhd from core_gen
src/ ccd_vita25K.vhd - add port video sync
ucf/ clock region for ccd lvds
src/
src/ for deres using only BUFG. ISE implementation - OK
src/ cleanup
sim/ add testbanch for deser_lvds_ccd.vhd + add deser_clock_gen.vhd
src/ deser_lvds_ccd.vhd - cleanup
add ReadMe.txt
src/ deser_lvds_ccd.vhd - change filling bit into generate gen_dout
sim/ change bit filling for tx data
cleanup