Add or1k tick timer register definitions
rtems_termios_puts: Copy and write more than one char at once

Renamed startXmit(), nToSend is unsigned, just check FL_ORCVXOF, no (void) cast anymore, compute nToSend in single if/else if/else.
score: PR2179: Fix initially locked PI mutex
lpc24xx/lpc17xx: lpc24xx_pin_set_function() keep LPC4088 W type pin in digital mode for non-analog function.

The problem wit incorrect switching of pins into analog mode manifestes
on LPC4088 based board.

LPC4088 implements pin P1.17 (ENET_MDIO) as new W type (digital pin
with analog option). The pin was listed as D category on LPC1788
which does not have analog mode control bit. If analog option is
not explicitly switched off on LPC4088 then the pin does not work
as digital pin.

Code tested on LPC1788 and no problems has been observed even that
manual specifies the IOCON_ADMODE field as reserved and should
be written as zero. But even RTEMS lpc24xx_gpio_config sets this
bit unconditionally.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>
BSP for TMS570LS31x Hercules Development Kit from TI (TMS570LS3137)

Included variants:
  tms570ls3137_hdk_intram - place code and data into internal SRAM
  tms570ls3137_hdk_sdram - place code into external SDRAM and data to SRAM
  tms570ls3137_hdk - variant prepared for stand-alone RTEMS aplication
                      stored and running directly from flash. Not working yet.

Chip initialization code not included in BSP.
External startup generated by TI's HalCoGen was used	for
testing and debugging.

More information about TMS570 BSP can be found at
  http://www.rtems.org/wiki/index.php/Tms570

Patch version 2
  - most of the formatting suggestion applied.
  - BSP converted to use clock shell
  - console driver "set attributes" tested. Baudrate change working
Patch version 3
  - more formatting changes.
  - removed leftover defines and test functions
Todo:
  refactor header files (name register fields)
Add new (first) OpenRISC BSP called or1ksim.

This BSP is intended to run on or1ksim (the main OpenRISC emulator).
Fixed version according to Joel comments from the mailing list.
libbsp/arm/acinclude.m4: Regenerate for tms570
Add new documentation section for OpenRISC CPU architecture.
or1k.t: Fix spelling errors
mpc55xx/misc/flash_support.c: Properly flush cache when writing.

    Also cleanup:
    * Remove un-needed interrupt disables.
    * Address errata "e989: FLASH: Disable Prefetch during programming and erase"
    * Use RTEMS_ARRAY_SIZE() macro instead of own macro.
Add configuration to detect toolset has sigaltstack() prototype
bsp/tms570: implemented support functions to satisfy complete tests build requirements.

This patch enables to build all RTEMS tests for tms570ls3137_hdk_sdram
BSP variant in in default build. Debug build with --enable-rtems-debug set
has succeed for samples subset of tests as well.
bsp/tms570: disable huge memory demanding tests for internal RAM build variant.

BSP completes build with tests and debug enabled for all three variants now

  tms570ls3137_hdk
  tms570ls3137_hdk_intram
  tms570ls3137_hdk_sdram

Even that all enabled tests builds for internal RAM variant, many
of them are expected to fail on hardware because whole tests
including code, data and runtime work area demands has to fit
into 256 kB of RAM.
libchip/dwmac: Make PHY address user configurable

This patch allows the user to configure the PHY address for the DWMAC
driver by giving a pointer to a dwmac_user_cfg structure to network
stack via rtems_bsdnet_ifconfig::drv_ctrl.
score: Add function to send a SMP message to a set of CPUs
score: Rename SMP broadcast message function

Change message type to unsigned long to match other SMP message functions.
bsp/sparc: Flush icache before first time enabling interrupts

A secondary processor might miss changes done to the trap table
if the instruction cache is not flushed. Once interrupts are enabled
any other required cache flushes can be ordered via the cache
manager.
score/sparc: Add comment on icache flush after trap table update

Changes to the trap table might be missed by other cores.
If the system state is up, the other cores can be notified
using SMP messages that they need to flush their icache.
If the up state has not been reached there is no need to
notify other cores. They will do an automatic flush of the
icache just after entering the up state, but before enabling
interrupts. Cache invalidation is required for both single
and multiprocessor systems.
bsp/sparc: Flush only instruction cache

The flush instruction on LEON flushes both the data and the instruction
cache. Flushing of just the instruction cache can be done by setting
the "flush instruction cache" bit in the cache control register.
score: Add SMP support to the cache manager

Adds functions that allows the user to specify which cores that should
perform the cache operation. SMP messages are sent to all the specified
cores and the caller waits until all cores have acknowledged that they
have flushed their cache. If CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING is
defined the instruction cache invalidation function will perform the
operation on all cores using the previous method.