Implement LD1/ST1 {3 regs . 16b}, [ea]  (no offset)


git-svn-id: svn://svn.valgrind.org/vex/trunk@2884 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Fix bogus-looking assertion.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2885 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Remove commented out junk which is never going to get used.
No functional change.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2886 8f6e269a-dfd6-0310-a8e1-e2731360e62c
arm64: implement:
LD3/ST3 (multi 3-elem structs, 3 regs, post index) (2d variants only)
pmul 16b_16b_16b, 8b_8b_8b


git-svn-id: svn://svn.valgrind.org/vex/trunk@2887 8f6e269a-dfd6-0310-a8e1-e2731360e62c
arm64: implement pmull{2}.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2888 8f6e269a-dfd6-0310-a8e1-e2731360e62c
The vector versions of the count leading zeros/sign bits primops
(Iop_Cls* and Iop_Clz*) misleadingly imply a signedness in the
incoming lanes.  Rename them to fix this.  Fixes #326026.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2889 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Rename the vector subparts-of-lanes-reversal IROps to names
that are easier to understand.  No functional change.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2890 8f6e269a-dfd6-0310-a8e1-e2731360e62c