Sink DwarfUnit::CURanges into DwarfCompileUnit

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221161 91177308-0d34-0410-b5e6-96231b3b80d8
Cleanup some unused or trivial functions in DwarfCompileUnit

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221164 91177308-0d34-0410-b5e6-96231b3b80d8
Remove the cortex-a9-mp CPU.

This CPU definition is redundant. The Cortex-A9 is defined as
supporting multiprocessing extensions. Remove its definition and
update appropriate tests.

LLVM defines both a cortex-a9 CPU and a cortex-a9-mp CPU. The only
difference between the two CPU definitions in ARM.td is that
cortex-a9-mp contains the feature FeatureMP for multiprocessing
extensions.

This is redundant since the Cortex-A9 is defined as having
multiprocessing extensions in the TRMs. armcc also defines the
Cortex-A9 as having multiprocessing extensions by default.

Change-Id: Ifcadaa6c322be0a33d9d2a39cfdd7da1d75981a7

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221166 91177308-0d34-0410-b5e6-96231b3b80d8
IR: MDNode => Value: Instruction::getAllMetadataOtherThanDebugLoc()

Change `Instruction::getAllMetadataOtherThanDebugLoc()` from a vector of
`MDNode` to one of `Value`.  Part of PR21433.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221167 91177308-0d34-0410-b5e6-96231b3b80d8
Normally an 'optnone' function goes through fast-isel, which does not
call DAGCombiner. But we ran into a case (on Windows) where the
calling convention causes argument lowering to bail out of fast-isel,
and we end up in CodeGenAndEmitDAG() which does run DAGCombiner.
So, we need to make DAGCombiner check for 'optnone' after all.

Commit includes the test that found this, plus another one that got
missed in the original optnone work.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221168 91177308-0d34-0410-b5e6-96231b3b80d8
Relax the LLVM_NOEXCEPT _MSC_VER version check back to 1900

Unconditional noexcept support was added in the VS 2013 Nov CTP. Given
that there have been three CTPs since then, I don't think we need
careful macro magic to target that specific tech preview. Instead,
target the major release version number of 1900, which corresponds to
the as-yet unreleased VS "14".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221169 91177308-0d34-0410-b5e6-96231b3b80d8
[Reassociate] Canonicalize negative constants out of expressions.

This gives CSE/GVN more options to eliminate duplicate expressions.
This is a follow up patch to http://reviews.llvm.org/D4904.

http://reviews.llvm.org/D5363

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221171 91177308-0d34-0410-b5e6-96231b3b80d8
Reapply: R600: Make sure to inline all internal functions

Function calls aren't supported yet.

This was reverted due to build breakages, which should be fixed now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221173 91177308-0d34-0410-b5e6-96231b3b80d8
EarlyCSE should ignore calls to @llvm.assume

EarlyCSE uses a simple generation scheme for handling memory-based
dependencies, and calls to @llvm.assume (which are marked as writing to memory
to ensure the preservation of control dependencies) disturb that scheme
unnecessarily. Skipping calls to @llvm.assume is legal, and the alternative
(adding AA calls in EarlyCSE) is likely undesirable (we have GVN for that).

Fixes PR21448.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221175 91177308-0d34-0410-b5e6-96231b3b80d8
[X86] 8bit divrem: Improve codegen for AH register extraction.

For 8-bit divrems where the remainder is used, we used to generate:
    divb  %sil
    shrw  $8, %ax
    movzbl  %al, %eax

That was to avoid an H-reg access, which is problematic mainly because
it isn't possible in REX-prefixed instructions.

This patch optimizes that to:
    divb  %sil
    movzbl  %ah, %eax

To do that, we explicitly extend AH, and extract the L-subreg in the
resulting register.  The extension is done using the NOREX variants of
MOVZX.  To support signed operations, MOVSX_NOREX is also added.
Further, this introduces a new SDNode type, [us]divrem_ext_hreg, which is
then lowered to a sequence containing a single zext (rather than 2).

Differential Revision: http://reviews.llvm.org/D6064


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221176 91177308-0d34-0410-b5e6-96231b3b80d8
MSVC requires redeclarations to repeat noexcept

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221177 91177308-0d34-0410-b5e6-96231b3b80d8
[ARM, inline-asm] Fix ARMTargetLowering::getRegForInlineAsmConstraint to return
register class tGPRRegClass if the target is thumb1.

This commit fixes a crash that occurs during register allocation which was
triggered when a virtual register defined by an inline-asm instruction had to
be spilled.
 
rdar://problem/18740489


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221178 91177308-0d34-0410-b5e6-96231b3b80d8
Add DwarfCompileUnit::BaseAddress to track the base address used by relative addressing in debug_ranges and debug_loc

This is one of a few steps to generalize range handling to include the
CU range (thus the CU's range list will be moved into the range list
list, losing track of the base address in the process), which means
generalizing ranges from both the skeleton and full unit under fission.

And... then I can used that generalized support for ranges in
fission+gmlt where there'll be a bunch more ranges in the skeleton.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221182 91177308-0d34-0410-b5e6-96231b3b80d8
[lit] Forward LD_PRELOAD to tests.

With this patch I can use asan to test the gold plugin without having
to build gold itself with asan.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221183 91177308-0d34-0410-b5e6-96231b3b80d8
[X86] Add debug print name for X86ISD::[US]MUL8. NFC-ish.

The opcodes were added in r220516, but I forgot to add the print names.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221185 91177308-0d34-0410-b5e6-96231b3b80d8
Push the CURangeList down into the skeleton CU (where available) rather than the full CU

So that it may be shared between skeleton/full compile unit, for CU
ranges and other ranges to be added for fission+gmlt.

(at some point we might want some kind of object shared between the
skeleton and full compile units for all those things we only want one of
in that scope, rather than having the full unit always look through to
the skeleton... - alternatively, we might be able to have the skeleton
pointer (or another, separate pointer) point to the skeleton or to the
unit itself in non-fission, so we don't have to special case its
absence)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221186 91177308-0d34-0410-b5e6-96231b3b80d8
InstCombine: Remove infinite loop caused by FoldOpIntoPhi

FoldOpIntoPhi could create an infinite loop if the PHI could potentially
reach a BB it was considering inserting instructions into.  The
instructions it would insert would eventually lead to other combines
firing which would, again, lead to FoldOpIntoPhi firing.

The solution is to handicap FoldOpIntoPhi so that it doesn't attempt to
insert instructions that the PHI might reach.

This fixes PR21377.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221187 91177308-0d34-0410-b5e6-96231b3b80d8
refactor duplicated code. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221191 91177308-0d34-0410-b5e6-96231b3b80d8
Handle ASAN_OPTIONS and UBSAN_OPTIONS in TestingConfig.py

Currently they are passed to tests of llvm itself, but not, for example, lld.

With this patch the options are visible in every test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221198 91177308-0d34-0410-b5e6-96231b3b80d8
[AArch64] Make function processLogicalImmediate more efficient. NFC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221199 91177308-0d34-0410-b5e6-96231b3b80d8