initiail commit for new passes: eliminate couter and backannotation remains
split nameAll
Merge branch 'master' of https://github.com/ucb-bar/chisel into rearrange_passes
move comp sorting into Driver
clasify clock and reset assignments as analyses
inferAll -> analysis
collectNodesIntoComp, findConsumers -> analysis
reimplement computeMemPorts, forceMatchingWidths, lowerNodes, removeTypeNodes
move findCombLoop into Backend and order Backend passes in elaborate
remove binding adding in traceNode
remove module resolution checks in traceNode
reimplement collectNodesIntoComps with Driver dfs
rearrage passes again
lowerNodes before custom transforms and temporary node naming
add bindings only in the verilog backend and give different names to temporary nodes in the c backend
fix bfs & dfs
clean up deprecated stuff
remove traceNodes
remove findConsumers in code generation
undo changes in the global bfs