ARM64: Generate better immediates for shifted ops

Improve code generated for immediate data processing operations where the shift
on the operation can be exploited to use fewer instructions for the immediate.

For example, Add(x0, x0, 0x1f7de) used to generate:
  movz x16, 0xf7de
  movk x16, 0x1, lsl #16
  add x0, x0, x16

now generates:
  movz x16, 0xfbef
  add x0, x0, x16, lsl #1

BUG=
R=ulan@chromium.org

Review URL: https://codereview.chromium.org/368313002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22246 ce2b1a6d-e550-0410-aec6-3dcde31c8c00