[ARM64,C++11] Range'ify use-lists iterators in address type promotion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206013 91177308-0d34-0410-b5e6-96231b3b80d8
[c++11] Range'ify use list loops in DAGCombiner.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206014 91177308-0d34-0410-b5e6-96231b3b80d8
[c++11] Range'ify use list loops in InstrEmitter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206015 91177308-0d34-0410-b5e6-96231b3b80d8
Implement depth_first and inverse_depth_first range factory functions.

Also updated as many loops as I could find using df_begin/idf_begin -
strangely I found no uses of idf_begin. Is that just used out of tree?

Also a few places couldn't use df_begin because either they used the
member functions of the depth first iterators or had specific ordering
constraints (I added a comment in the latter case).

Based on a patch by Jim Grosbach. (Jim - you just had iterator_range<T>
where you needed iterator_range<idf_iterator<T>>)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206016 91177308-0d34-0410-b5e6-96231b3b80d8
[yaml2obj][ELF] ELF Relocations Support.

The patch implements support for both relocation record formats: Elf_Rel
and Elf_Rela. It is possible to define relocation against symbol only.
Relocations against sections will be implemented later. Now yaml2obj
recognizes X86_64, MIPS and Hexagon relocation types.

Example of relocation section specification:
Sections:
- Name: .text
  Type: SHT_PROGBITS
  Content: "0000000000000000"
  AddressAlign: 16
  Flags: [SHF_ALLOC]

- Name: .rel.text
  Type: SHT_REL
  Info: .text
  AddressAlign: 4
  Relocations:
    - Offset: 0x1
      Symbol: glob1
      Type: R_MIPS_32
    - Offset: 0x2
      Symbol: glob2
      Type: R_MIPS_CALL16

The patch reviewed by Michael Spencer, Sean Silva, Shankar Easwaran.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206017 91177308-0d34-0410-b5e6-96231b3b80d8
Fix use-after-free bug caught by address sanitizer:

http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap/builds/2959

The location string is returned as a std::string, not a StringRef.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206032 91177308-0d34-0410-b5e6-96231b3b80d8
Revert: r205182 - llvm/test/MC/Mips/mips64r2/valid-xfail.s: This REQUIRES asserts. Seems it doesn't fail with -Asserts.

This was most likely caused by an uninitialized value and the relevant code was re-written in r205292. Reverting to see if it still fails on any of the buildbots.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206033 91177308-0d34-0410-b5e6-96231b3b80d8
SelectionDAG: Factor ISD::MUL lowering code out of DAGTypeLegalizer

This code has been moved to a new function in the TargetLowering
class called expandMUL().  The purpose of this is to be able
to share lowering code between the SelectionDAGLegalize and
DAGTypeLegalizer classes.

No functionality changed intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206036 91177308-0d34-0410-b5e6-96231b3b80d8
SelectionDAG: Use helper function to improve legalization of ISD::MUL

The TargetLowering::expandMUL() helper contains lowering code extracted
from the DAGTypeLegalizer and allows the SelectionDAGLegalizer to expand more
ISD::MUL patterns without having to use a library call.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206037 91177308-0d34-0410-b5e6-96231b3b80d8
Move ExtractVectorElements to SelectionDAG.

This seems generally useful, and makes sense to
go along with SplitVector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206041 91177308-0d34-0410-b5e6-96231b3b80d8
Debug info: Store the DIVariable in DebugLocEntry also for constants,
so DwarfDebug::emitDebugLocEntry can emit them with the correct signedness.

rdar://problem/15928306

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206042 91177308-0d34-0410-b5e6-96231b3b80d8
Fix shift by constants for vector.

ashr <N x iM>, <N x iM> M -> undef

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206045 91177308-0d34-0410-b5e6-96231b3b80d8
Add some CHECKs to this testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206046 91177308-0d34-0410-b5e6-96231b3b80d8
Don't lose the thumb bit by using relocations with sections.

This fixes a regression from r205076.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206047 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Refactor SOPC classes slightly.

Better match what is done for VOPC to eventually
prefer selecting these.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206048 91177308-0d34-0410-b5e6-96231b3b80d8
[Register Coalescer] Fix wrong live-range information with rematerialization.
When rematerializing an instruction that defines a super register that would be
used by a physical subregisters we use the related physical super register for
the definition.
To keep the live-range information accurate, all the defined subregisters must be
marked as dead def, otherwise the register allocation may miss some
interferences.

Working on a reduced test-case!

<rdar://problem/16582185>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206060 91177308-0d34-0410-b5e6-96231b3b80d8
Remove redundant symbolization support from MCDisassembler interface.

MCDisassembler has an MCSymbolizer member that is meant to take care of
symbolizing during disassembly, but it also has several methods that enable the
disassembler to do symbolization internally (i.e. without an attached symbolizer
object). There is no need for this duplication, but ARM64 had been making use of
it. This patch moves the ARM64 symbolization logic out of ARM64Disassembler and
into an ARM64ExternalSymbolizer class, and removes the duplicated MCSymbolizer
functionality from the MCDisassembler interface. Symbolization will now be
done exclusively through MCSymbolizers.

There should be no impact on disassembly for any platform, but this allows us to
tidy up the MCDisassembler interface and simplify the process of (and invariants
related to) disassembler setup.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206063 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Check if a sextload should be used for parameter loads.

Through some oddity where truncate (sextload x) isn't folded into
an anyextload for vectors, the sextload remains if the
vector isn't immediately scalarized. This keeps the expected
zextload instructions in the kernel-args test when small type
vectors aren't scalarized.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206070 91177308-0d34-0410-b5e6-96231b3b80d8
[RegAllocGreedy][Last Chance Recoloring] Addition of
-fexhaustive-register-search option to allow an exhaustive search during last
chance recoloring.

This is related to PR18747

Patch by MAYUR PANDEY <mayur.p@samsung.com>. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206072 91177308-0d34-0410-b5e6-96231b3b80d8
[RegAllocGreedy][Last Chance Recoloring] Change the name of the exhaustive search option.
fexhaustive-register-search => exhaustive-register-search
'f' is a Clang thing!

This is related to PR18747.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206075 91177308-0d34-0410-b5e6-96231b3b80d8