Updated the RDHWR instruction with
- 0 now returning procID
- 30 total core - 1
Introducing a per core coherent private dcache L1
Experienced with hash functions for l1 dcache index/tag
Adding a cheri specific memory subsystem
Added cache CHERI hierarchy
Fixed L2 update in CHERI memory + log info
Refining CHERI cache hierarchy and logging info
Fixed CHERI coherence mechanism on L2 evictions
Added short tags check for L1 invalidates
Added privatel1-sharedl2 from cheri to standard build
Updated cheri memory subsystem to be capability aware
Updated logged info + cache coherence protocol more selective
Introducing pointer prefetching in the L2
Adding big lines (1024bits) in the L2
Fixed pointer prefetch and coherence in single core
Added prefetch depth command line option + log info