[AArch64]Fix the problem can't select concat_vectors of two v1i32 types.
Also fix the problem can't select scalar_to_vector from f32 to v2f32/v4f32.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199461 91177308-0d34-0410-b5e6-96231b3b80d8
[AArch64 NEON] Custom lower conversion between vector integer and vector floating point if element bit-width doesn't match.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199462 91177308-0d34-0410-b5e6-96231b3b80d8
[AArch64]Fix the problem can't select f16_to_f32 and f32_to_f16.
Also add copy support for FPR16.
Also add a missing test case file belongs to commit r197361.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199463 91177308-0d34-0410-b5e6-96231b3b80d8
Replace duplicated code with a existing helper function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199468 91177308-0d34-0410-b5e6-96231b3b80d8
VEX_PREFIX_66 doesn't need to set the hasOpSize flag since VEX instructions don't use the size fields it controls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199470 91177308-0d34-0410-b5e6-96231b3b80d8
Fix intel syntax for 64-bit version of FXSAVE/FXRSTOR to use '64' suffix instead of 'q'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199474 91177308-0d34-0410-b5e6-96231b3b80d8
Teach X86 asm parser to understand 'ZMMWORD PTR' in Intel syntax.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199476 91177308-0d34-0410-b5e6-96231b3b80d8
Teach x86 asm parser to handle 'opaque ptr' in Intel syntax.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199477 91177308-0d34-0410-b5e6-96231b3b80d8
Add OpSize16 flags to 32-bit CRC32 instructions so they can be encoded correctly in 16-bit mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199478 91177308-0d34-0410-b5e6-96231b3b80d8
Switch a few instructions to use RI instead I so they don't require REX_W to be explicitly specified.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199479 91177308-0d34-0410-b5e6-96231b3b80d8
Add the test for libstdc++ versions newer than 4.6 so we don't
accidentally pick that up while using Clang and run into subtle bugs
down the road related to C++11 features not fully implemented in that
version of the standard library.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199484 91177308-0d34-0410-b5e6-96231b3b80d8
[AArch64 NEON] Expand vector for UDIV/SDIV/UREM/SREM/FREM as neon doesn't support these operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199485 91177308-0d34-0410-b5e6-96231b3b80d8
[PM] Remove the preverifier and directly compute the DominatorTree for
the verifier after ensuring the CFG is at least usefully formed.

This fixes a number of problems:
1) The PreVerifier was missing the controls the Verifier provides over
   *how* an invalid module is handled -- it just aborted the program!
   Now it uses the same logic as the Verifier which is significantly
   more library-friendly.
2) The DominatorTree used previously could have been cached and not
   updated due to bugs in prior passes and we would silently use the
   stale tree. This could cause dominance errors to not be as quickly
   diagnosed.
3) We can now (in the next patch) pull the functionality of the verifier
   apart from the pass infrastructure so that you can verify IR without
   having any form of pass manager. This in turn frees the code to share
   logic between old and new pass manager variants.

Along the way I fixed at least one annoying bug -- the state for
'Broken' wasn't being cleared from run to run causing all functions
visited after the first broken function to be marked as broken
regardless of whether *they* were a problem. Fortunately, I don't really
know much of a way to observe this peculiarity.

In case folks are worried about the runtime cost, its negligible.
I looked at running the entire regression test suite (which should be
a relatively good use of the verifier) before and after but was unable
to even measure the time spent on the verifier and there was no
regresion from before to after. I checked both with debug builds and
optimized builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199487 91177308-0d34-0410-b5e6-96231b3b80d8
[asan] extend asan-coverage (still experimental).
 - add a mode for collecting per-block coverage (-asan-coverage=2).
   So far the implementation is naive (all blocks are instrumented),
   the performance overhead on top of asan could be as high as 30%.
 - Make sure the one-time calls to __sanitizer_cov are moved to function buttom,
   which in turn required to copy the original debug info into the call insn.

Here is the performance data on SPEC 2006
(train data, comparing asan with asan-coverage={0,1,2}):

                             asan+cov0     asan+cov1      diff 0-1    asan+cov2       diff 0-2      diff 1-2
       400.perlbench,        65.60,        65.80,         1.00,        76.20,         1.16,         1.16
           401.bzip2,        65.10,        65.50,         1.01,        75.90,         1.17,         1.16
             403.gcc,         1.64,         1.69,         1.03,         2.04,         1.24,         1.21
             429.mcf,        21.90,        22.60,         1.03,        23.20,         1.06,         1.03
           445.gobmk,       166.00,       169.00,         1.02,       205.00,         1.23,         1.21
           456.hmmer,        88.30,        87.90,         1.00,        91.00,         1.03,         1.04
           458.sjeng,       210.00,       222.00,         1.06,       258.00,         1.23,         1.16
      462.libquantum,         1.73,         1.75,         1.01,         2.11,         1.22,         1.21
         464.h264ref,       147.00,       152.00,         1.03,       160.00,         1.09,         1.05
         471.omnetpp,       115.00,       116.00,         1.01,       140.00,         1.22,         1.21
           473.astar,       133.00,       131.00,         0.98,       142.00,         1.07,         1.08
       483.xalancbmk,       118.00,       120.00,         1.02,       154.00,         1.31,         1.28
            433.milc,        19.80,        20.00,         1.01,        20.10,         1.02,         1.01
            444.namd,        16.20,        16.20,         1.00,        17.60,         1.09,         1.09
          447.dealII,        41.80,        42.20,         1.01,        43.50,         1.04,         1.03
          450.soplex,         7.51,         7.82,         1.04,         8.25,         1.10,         1.05
          453.povray,        14.00,        14.40,         1.03,        15.80,         1.13,         1.10
             470.lbm,        33.30,        34.10,         1.02,        34.10,         1.02,         1.00
         482.sphinx3,        12.40,        12.30,         0.99,        13.00,         1.05,         1.06


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199488 91177308-0d34-0410-b5e6-96231b3b80d8
[PM] [cleanup] Rename some of the Verifier's members, re-arrange them,
and tweak comments prior to more invasive surgery. Also clean up some
other non-doxygen comments, and run clang-format over the parts that are
going to change dramatically in subsequent commits so that those don't
get cluttered with formatting changes.

No functionality changed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199489 91177308-0d34-0410-b5e6-96231b3b80d8
Add MLA alias for ARMv4 support.

Fix MLA defs to use register class GPRnopc.
Add encoding tests for multiply instructions.
(Alias for MUL/SMLAL/UMLAL added by r199026.)

Patch by Zhaoshi.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199491 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][sched] Split IIHiLo into II_MFHI_MFLO and II_MTHI_MTLO

No functional change since the InstrItinData's have been duplicated.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199493 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][sched] Split IIImul and IIImult into subclasses.

IIImul -> II_MUL
IIImult -> II_MULT, II_MULTU, II_MADD, II_MADDU, II_MSUB, II_MSUBU, II_DMULT, II_DMULTU

No functional change since the InstrItinData's have been duplicated.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199495 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Split IIIdiv int II_DIV, II_DIVU, II_DDIV, and II_DDIVU

No functional change since the InstrItinData's were duplicated



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199497 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][msa] Correct pattern for LSA

Summary:
$rs and $rt were the wrong way round in the .td and the testcase wasn't
strict enough to detect the mistake.

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D2554

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199498 91177308-0d34-0410-b5e6-96231b3b80d8