ASoC: pcm: update the start-up sequence for playback

Codec should be started before the adsp to ensure that there is no data
loss during playback.Current sequence enables the adsp first followed by
codec.This change updates the sequence prevent any playback data loss.

Change-Id: Iaf01d153f41a2f94d302ae7f4c1c98b1361dd24f
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
ASoC: msm: qdsp6v2: fix rtac command failure

In rtac driver, while sending PP_Params for ADM copp
to DSP, token needs to be port_id whereas coppid is used.
Replace it with port_id to avoid failure in command
and timeout issue.

Change-Id: I77ab13ea14e8d6c25514bdeed24db37ef8113a75
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
ASoC: msm: Fix ADM GET PARAM callback

Add size check on inband get param call and do
not process inband if RTAC is active.

Change-Id: I2c099f5ea254a214f224dda556773a7fe6754fe5
CRs-fixed: 548397
Signed-off-by: Ben Romberger <bromberg@codeaurora.org>
ASoC: msm: Add bounds checking to ADM get params

Add additional bounds checking to ADM get params.
Validate that all buffer sizes are valid before
dereferencing.

Change-Id: If7c7a5ae6a56812e9c4a11a38c9bdc78f42d09f3
Signed-off-by: Ben Romberger <bromberg@codeaurora.org>
ASoC: msm: qdsp6v2: Check for null pointers

Add check for null data pointer in
adm_callback() and log error message if
true.

CRs-Fixed: 575222
Change-Id: I88a4d19cc2e78610249e404bce93831557995fab
Signed-off-by: Kenneth Westfield <kwestfie@codeaurora.org>
ASoC: msm: qdsp6v2: Avoid DS1 and SRS topology on low latency path

Currently, the low latency path go through tuning of the post
processing with the default as well as third party post
processing topologies such as DS1 and TruMedia topology. Avoid
enabling the DS1 and TruMedia topology on low latency path
retaining the tuning functionality on the default topology.

CRs-Fixed: 643857
Change-Id: I8ae6b4ecb0be530c8d72218d39498cff7f8a7fd9
Signed-off-by: Subhash Chandra Bose Naripeddy <snariped@codeaurora.org>
ASoC: msm: Use 16K sample rate for RFECNS

To enable record with an RFECNS device use a 16K
sample rate

Change-Id: Ib9c6a4605f6a7f9e5f4c25280e0cc646459815fc
Signed-off-by: Ben Romberger <bromberg@codeaurora.org>
ASoc: msm: qdsp6v2: Fix for NULL check

- Required check added for NULL pointer

CRs-fixed: 583939
Change-Id: I8b079c42ef06af9a817dc830c5f2d3c785232aa7
Signed-off-by: Mingming Yin <mingming@codeaurora.org>
Signed-off-by: Mohammad Johny Shaik <mjshai@codeaurora.org>
CHROMIUM: arch/arm: Remove duplicated code in syscall_trace

This is breaking the ptrace syscall on ARM. Looks like a mismerge in
5ea62181 ("CHROMIUM: arch/arm: move secure_computing into trace").

TEST=ran "strace true"
BUG=chromium-os:36102

Change-Id: Ic377577216bed3672201ca71604f650c1b8b3f0c
Signed-off-by: Michael Spang <spang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/38602
Reviewed-by: Doug Anderson <dianders@chromium.org>
ARM: bitops: prefetch the destination word for write prior to strex

The cost of changing a cacheline from shared to exclusive state can be
significant, especially when this is triggered by an exclusive store,
since it may result in having to retry the transaction.

This patch prefixes our atomic bitops implementation with prefetchw,
to try and grab the line in exclusive state from the start. The testop
macro is left alone, since the barrier semantics limit the usefulness
of prefetching data.

Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>

ARM: 7907/1: lib: delay-loop: Add align directive to fix BogoMIPS calculation

Currently mx53 (CortexA8) running at 1GHz reports:
Calibrating delay loop... 663.55 BogoMIPS (lpj=3317760)

Tom Evans verified that alignments of 0x0 and 0x8 run the two instructions of __loop_delay in one clock cycle (1 clock/loop), while alignments of 0x4 and 0xc take 3 clocks to run the loop twice. (1.5 clock/loop)

The original object code looks like this:

00000010 <__loop_const_udelay>:
  10:	e3e01000 	mvn	r1, #0
  14:	e51f201c 	ldr	r2, [pc, #-28]	; 0 <__loop_udelay-0x8>
  18:	e5922000 	ldr	r2, [r2]
  1c:	e0800921 	add	r0, r0, r1, lsr #18
  20:	e1a00720 	lsr	r0, r0, #14
  24:	e0822b21 	add	r2, r2, r1, lsr #22
  28:	e1a02522 	lsr	r2, r2, #10
  2c:	e0000092 	mul	r0, r2, r0
  30:	e0800d21 	add	r0, r0, r1, lsr #26
  34:	e1b00320 	lsrs	r0, r0, #6
  38:	01a0f00e 	moveq	pc, lr

0000003c <__loop_delay>:
  3c:	e2500001 	subs	r0, r0, #1
  40:	8afffffe 	bhi	3c <__loop_delay>
  44:	e1a0f00e 	mov	pc, lr

After adding the 'align 3' directive to __loop_delay (align to 8 bytes):

00000010 <__loop_const_udelay>:
  10:	e3e01000 	mvn	r1, #0
  14:	e51f201c 	ldr	r2, [pc, #-28]	; 0 <__loop_udelay-0x8>
  18:	e5922000 	ldr	r2, [r2]
  1c:	e0800921 	add	r0, r0, r1, lsr #18
  20:	e1a00720 	lsr	r0, r0, #14
  24:	e0822b21 	add	r2, r2, r1, lsr #22
  28:	e1a02522 	lsr	r2, r2, #10
  2c:	e0000092 	mul	r0, r2, r0
  30:	e0800d21 	add	r0, r0, r1, lsr #26
  34:	e1b00320 	lsrs	r0, r0, #6
  38:	01a0f00e 	moveq	pc, lr
  3c:	e320f000 	nop	{0}

00000040 <__loop_delay>:
  40:	e2500001 	subs	r0, r0, #1
  44:	8afffffe 	bhi	40 <__loop_delay>
  48:	e1a0f00e 	mov	pc, lr
  4c:	e320f000 	nop	{0}

, which now reports:
Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)

Some more test results:

On mx31 (ARM1136) running at 532 MHz, before the patch:
Calibrating delay loop... 351.43 BogoMIPS (lpj=1757184)

On mx31 (ARM1136) running at 532 MHz after the patch:
Calibrating delay loop... 528.79 BogoMIPS (lpj=2643968)

Also tested on mx6 (CortexA9) and on mx27 (ARM926), which shows the same
BogoMIPS value before and after this patch.

Reported-by: Tom Evans <tom_usenet@optusnet.com.au>
Suggested-by: Tom Evans <tom_usenet@optusnet.com.au>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: 7404/1: cmpxchg64: use atomic64 and local64 routines for cmpxchg64

The cmpxchg64 routines for ARMv6+ CPUs replicate inline assembly that
already exists for atomic64 operations. Furthermore, the cmpxchg64 code
uses the "memory" constraint in the clobber list rather than identifying
the region of memory that is actually modified.

This patch replaces the ARMv6+ cmpxchg64 code with macros that expand to
the atomic64_ and local64_ variants, casting the pointer parameter to
the appropriate container type.

Cc: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: 7720/1: ARM v6/v7 cmpxchg64 shouldn't clear upper 32 bits of the old/new value

The implementation of cmpxchg64() for the ARM v6 and v7 architecture
casts parameter 2 and 3 (the old and new 64bit values) to an unsigned
long before calling the atomic_cmpxchg64() function. This clears
the top 32 bits of the old and new values, resulting in the wrong
values being compare-exchanged. Luckily, this only appears to be used
for 64-bit sched_clock, which we don't (yet) have on ARM.

This bug was introduced by commit 3e0f5a15f500 ("ARM: 7404/1: cmpxchg64:
use atomic64 and local64 routines for cmpxchg64").

Cc: <stable@vger.kernel.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Jaccon Bastiaansen <jaccon.bastiaansen@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: 7852/1: cmpxchg: implement barrier-less cmpxchg64_local

Our cmpxchg64 macros are wrappers around atomic64_cmpxchg. Whilst this is
great for code re-use, there is a case for barrier-less cmpxchg where it
is known to be safe (for example cmpxchg64_local and cmpxchg-based
lockrefs).

This patch introduces a 64-bit cmpxchg implementation specifically
for the cmpxchg64_* macros, so that it can be later used by the lockref
code.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: 7853/1: cmpxchg: implement cmpxchg64_relaxed

This patch introduces cmpxchg64_relaxed for arm, which performs a 64-bit
cmpxchg operation without barrier semantics. cmpxchg64_local is updated
to use the new operation.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: 7984/1: prefetch: add prefetchw invocations for barriered atomics

After a bunch of benchmarking on the interaction between dmb and pldw,
it turns out that issuing the pldw *after* the dmb instruction can
give modest performance gains (~3% atomic_add_return improvement on a
dual A15).

This patch adds prefetchw invocations to our barriered atomic operations
including cmpxchg, test_and_xxx and futexes.

Change-Id: Id6ebfe82ff9578c27e2b745e2cce167200112606
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
cpuidle: check for need_resched() after the idle entry trace event

trace_cpu_idle_rcuidle() can end up waking ksoftirqd under certain
conditions. Since there is no check for need_resched() following
this wake up, the cpu ends up going into an idle state despite there
being a runnable task on that runqueue. Furthermore, since the
resched flag is set, any sucessive waking up tasks on the idle cpu
will not result in an IPI being sent to that cpu. Consequently tasks
on that runqueue will starve until the cpu exits idle by itself. Fix
this problem by adding a need_resched() check after the idle entry
trace event.

A side effect of this change is that the idle trace entry and exit
event may be recorded for an extremely short duration even though
the cpu does not actually enter idle.

Change-Id: I370c39a1e39ecd829e44ac783b4888a00ab05eae
Signed-off-by: Syed Rameez Mustafa <rameezmustafa@codeaurora.org>
mm: do not sleep in balance_pgdat if there's no i/o congestion

On a 4GB RAM machine, where Normal zone is much smaller than DMA32 zone,
the Normal zone gets fragmented in time.  This requires relatively more
pressure in balance_pgdat to get the zone above the required watermark.
Unfortunately, the congestion_wait() call in there slows it down for a
completely wrong reason, expecting that there's a lot of
writeback/swapout, even when there's none (much more common).  After a
few days, when fragmentation progresses, this flawed logic translates to
a very high CPU iowait times, even though there's no I/O congestion at
all.  If THP is enabled, the problem occurs sooner, but I was able to
see it even on !THP kernels, just by giving it a bit more time to occur.

The proper way to deal with this is to not wait, unless there's
congestion.  Thanks to Mel Gorman, we already have the function that
perfectly fits the job.  The patch was tested on a machine which nicely
revealed the problem after only 1 day of uptime, and it's been working
great.

Change-Id: I7002ad592243327312139a0de60231c4dc51f6fb
Signed-off-by: Zlatko Calusic <zlatko.calusic@iskon.hr>
Acked-by: Mel Gorman <mgorman@suse.de>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
ASoC: msm: qdsp6v2: check proxy port is open when closing

The current logic opens the afe proxy port only if the
proxy instance virtual port is opened. If only
pcm instance virtual port is opened and a close of the
afe proxy port is attempted, this causes the device to
crash due to a wait event timeout as the driver tries
to close an unopened afe port.
The change ensures that only if both the virtual ports
are opened, which in effect starts the proxy port,
the afe close commands for the proxy port is sent to DSP,
else return immediately.

Change-Id: I9450001c608208f3d8da22b2881a88db1c21d950
Signed-off-by: Aravind Kumar <akumark@codeaurora.org>
ASoC: msm: qdsp6v2: requeue read buffers in mmap device switch

When device switch happens, ASM might return a 0 length
buffer. For MMAP style capture cases, buffers need to be
re-queued at the event handler for this case, otherwise
ASM will have no buffers to read data into after the
device is over successful.

CRs-fixed: 700614
Change-Id: I2b8930a3058bbe3979405d5de04d3371291db42d
Signed-off-by: Banajit Goswami <bgoswami@codeaurora.org>
ASoC: msm: audio-effects: improve logging

Make logs more meaningful by logging values where ever
applicable.

Change-Id: I0fd0e62e543480762096d64c7ee7c92eb1204126
Signed-off-by: Dhananjay Kumar <dhakumar@codeaurora.org>
ASoC: msm: qdsp6v2: Cleanup of compress offload drivers

Clean up the format specifiers for compress offload drivers
and add compat ioctl support

Change-Id: I0829830336ec62c66658d6a5199d73b61249f791
Signed-off-by: Damir Didjusto <damird@codeaurora.org>
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
Revert "CHROMIUM: arch/arm: Remove duplicated code in syscall_trace"

This reverts commit 795a3623644f0fbfb7df8dd7b4119a47fb3297d9.
rtc: qpnp-rtc: Sets RTC time correctly

Currently RTC driver is not setting the RTC time
correctly. RTC H/w needs to be disabled before the
writes, and then re-enabled after the writes are completed.

Change-Id: I4f66a2ea5b8ba52a5e9dcf21da7a09c36b1c9074
CRs-Fixed: 610221
Signed-off-by: Mohit Aggarwal <maggarwa@codeaurora.org>
rtc: qpnp-rtc: Set alarm control register properly

RTC Alarm enable bit does not get conserved during
RTC probe function. This patch fixes that issue.

CRs-Fixed: 636652
Change-Id: I28203b8e301510d34d2e726c0bd25e78737f7524
Signed-off-by: Mohit Aggarwal <maggarwa@codeaurora.org>
qpnp-rtc: clear alarm register when rtc irq is disabled

The rtc alarm register should be cleared when the rtc irq is
disabled

Change-Id: I97a8bf989ff610093240a6b308a297702da6cb89
Signed-off-by: Xiaocheng Li <lix@codeaurora.org>