Checkpoint write-through dcache implementation
Merge branch 'master' into v2-write-through

Conflicts:
	rtl/v2/core/dcache_data_stage.v
	rtl/v2/core/instruction_pipeline.v
	rtl/v2/core/writeback_stage.v
Checkpoint: switch to request/response interface
Remove obsolete file. Fix uninitalized signal.
Fix a bunch of bugs and cleanup.
Missing file
Rename l2_cache_sim to sim_l2_cache to be consistent with other mock modules (prefixed with sim_)
Add boilerplate
More cache implementation
- Fix issues with write combining: a lot of logic was still assuming it couldn't
combine if there was an entry queued.
- Plumb synchronized signal into l1_miss_queue and avoid read combining synchronized
requests.
Cleanup and some comments
Implement load synchronized.
- Always take a cache miss on the first access to a request will be sent to L2 cache
- Pass synchronized flag to L2 interface
Make sim L2 cache handle synchronized load requests
Remove testbench code to autoflush L1 cache, since it is now write through
Fix store buffer race condition

Data could be write combined in the same cycle it was sent to the L2
cache. In this case, the write would be lost.
Dump hex dump delta when memory contents do not match
Rename signals to be clearer
Support sending synchronized store request
Checkpoint: roughed in synchronized store support
Fix synchronized store bugs
Synchronized load store works