VL: extended support for SystemVerilog ansi-style port declarations.

This implements parsing support for most of ANSI-style port declarations,
including interface ports.  A few things are not yet implemented, esp.  ref
ports, interconnect ports, and default values on ports.  The parts that are
implemented seem pretty solid and try to closely adhere to the standard.

The definition of vl-port-p structures is extended to support interface ports.
Most transforms don't yet understand these, and will simply cause fatal errors
if interface ports are used.  This situation may improve once we extend
scopestack to understand interfaces.

Also added some more failtests.
vl toolkit interfacing tweaks

 - Tweak vl-load to avoid redundant search-paths/extensions, and to understand
   that the user means the same thing when he says to use ".foo" or "foo" as
   the file extension.

 - Tweak toolkit to produce a break and a backtrace on errors, instead of just
   a backtrace.
VL: add sizing support for assignments/port connections of subranges of unpacked arrays
merge
VL: hack for faster warning printing, warning elision for report cards.