Fix for GitHub issue 19 : incorrect handling of large shift values.

For shift operations evaluated at compile time, the compiler was converting
the right operand to a native unsigned long value. If the operand exceeded
the size of an unsigned long, excess bits were discarded, which could lead
to an incorrect result.

The fix I've chosen is to add an as_unsigned() function to the verinum class
which returns the maximum unsigned value if the internal verinum value is
wider than the native unsigned type. This then naturally gives the correct
result for shifts, as the verinum bit width is also an unsigned value.

I've changed the as_ulong() and as_ulong64() functions to do likewise, as
this is more likely to either give the correct behaviour or to give some
indication that an overflow has occurred where these functions are used.
Fix invalid optimisations in tgt-vvp.

The vvp code generator was optimising away adds and subtracts where one
operand was a constant zero. This is not valid for 4-state arithmetic.
It was also optimising away multiplies by a constant zero - but in this
case getting it wrong and effectively multiplying by 1.
Fix space issue
Remove compile warning
Merge branch 'master' of git://github.com/steveicarus/iverilog