FogBugz #174257: Enhance fpga2sdram bridge release sequence

Enhance the fpga2sdram bridge release sequence to support
asymmetric multiprocessing (AMP) use case. The master in FPGA
might sending transaction to fpga2sdram bridge before the bridge
is enabled. This enhancement will ensure the transaction will
be back pressured and continued normally once the bridge is enabled.

Signed-off-by: Chin Liang See <clsee@altera.com>
FogBugz #173924: Adding DMA PL330 support

To add the driver support for DMA PL330 that located within HPS. The
driver does have high level function which enable memory-to-memory,
memory-to-peripheral and peripheral-to-memory transfer. It also
include a memory scrubbing function which write zeroes to
the assigned memory region

Signed-off-by: Chin Liang See <clsee@altera.com>
FogBugz #173924: Adding SDRAM ECC Scrubbing using DMA

User can optional enable the Preloader to scrub the SDRAM memory
to initialize the SDRAM ECC bits. This is to enable subsequent
software that running on SDRAM enable the SDRAM ECC interrupt.

To do the scrubbing, DMA is used to speed up the scrubbing speed.
At same time, the DMA run in parallel while Preloader loading
the subsequent boot image from flashes.

To scrub the whole 1GB memory, it took 1446ms. As comparison,
scrubbing using processor and memset function is taking 13s.

Signed-off-by: Chin Liang See <clsee@altera.com>
FogBugz #148005: Enhance Cyclone V MPU clock to 925MHz

Enhance the Cyclone V MPU clock from 800MHz to 925MHz. This is
to align with the new Cyclone V dev kit which is using C6 speed
grade parts.

Signed-off-by: Chin Liang See <clsee@altera.com>