1. For hw timing test
2. Because of the code size limitation, I comment the flash bank ouput log
3. Change the version to 2.0.3
code size optimization
remove unnecessary judgement
add a 15 sec check before pltrst pull high to prevent pci-e sw reboot
wrong deactive pin
add 5 sec delay if both na and nb rst is high
05191434: prevent idt_rst pull high before na_rst and rb_rst down to low
05210528: check s3 in each loop