drop io back to 32mhz to see if it fixes timing.
cut shadowram to 128KB to reduce access time.
fix simulate target (forgot to put dependencies back on).
put IO and CPU both on 48MHz
put uart monitor at 48MHz to match CPU to simplify timing between
the two.
add more drive stages to video debug registers to improve timing.
drive debug signals to ioclock side of VIC-IV before presenting them
to relax timing demands.
try to flatten logic for reading VIC-IV registers.
fix a bug with extended background mode.