mdss: display: edp continuous splash support.

Both edp main link clock and pixel clock are source from PLL.
This patch add edp clock nodes into system clock tree so that
both main link clock and pixel clock are configured properly
to support different panels with different resolution. Edp
related clocks handoff from bootloader are supported.

Change-Id: I6e4096beb9bff0d39f4f850bbc6d2157ac42e524
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: Panwar Vivek <vpanwa@codeaurora.org>

Signed-off-by: Manish Kumar <manishku@codeaurora.org>

Conflicts:
	drivers/video/msm/mdss/mdss_edp.c
msm: mdss: Sanitize read of panel properties

Check panel property's values properly before operating on
them.

CRs-Fixed: 562887
Change-Id: I26ce51e8b3a8e9328e7b6370b9c56d67fcdd1901
Signed-off-by: Mayank Chopra <makchopra@codeaurora.org>
msm: mdss: Sanitize read of panel properties some more
msm: mdss: perform proper clock handoff during cont. splash screen

During continuous splash screen need to ensure clocks are properly ref
counted once and released once handoff has happened. Doing it in
different places can lead to improper order and cause clocks to be
disabled. Fix this by centralizing this into footswitch ctrl which is
called when continous splash screen is enabled.

Change-Id: I17f3d5517d9a0583221fdb5c354bf1992ddeddbd
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
Signed-off-by: Pawan Kumar <pavaku@codeaurora.org>
msm: mdss: implement overlay prepare ioctl

Overlay prepare will allow a full frame with multiple overlays to be
configured at once and perform frame level checks before being pushed to
display. This function guarantees that if the call is successful, the
frame can be displayed successfully on the screen when display commit is
called.

Change-Id: I276b6fe3e0a872a2e93170f3cea1002d3ce0dac9
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
Signed-off-by: Anusha Koduru <kanusha@codeaurora.org>
msm: mdss: dsi-1 as master clock controller at split display case

During split display case, both dsi controllers share the same
dsi pll(dsi0) dsi-0 clock need to be enabled before dsi-1 and disabled
in the reverse order. This mechanism helps using a unified clock control
logic.

Change-Id: I9fe0095b0427c9c2b7fd84c3179bc8364049cce4
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
msm: mdss: Add support for ULPS mode for DSI

For smart panels that can refresh display from their internal
RAMs, it is possible to configure the DSI clock and data lanes
in Ultra Low Power State (ULPS) during idle static screen
usecase. Add support for this feature.

[myfluxi: Adapt to hammerhead]

Change-Id: I4e94d6a0201262f0675322efc9e39dd93c86edda
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
msm: mdss: Turn off MDP GDSC in idle screen for cmd mode panels

For command mode panels, the DSI lanes can be configured to an
Ultra Low Power State (ULPS) during idle screen use case. In such
cases, it is possible to turn off the MDP GDSC as MDP is completely
idle. This would result in reducing any leakage current. Add
support for this feature.

[myfluxi: Fix-up for hammerhead]

Change-Id: Ic4074f9e12a27fe0fbe95219ffaa2f466abee307
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
arm/dt: hammerhead: Enable ULPS mode