score: Add function to send a SMP message to a set of CPUs
score: Rename SMP broadcast message function

Change message type to unsigned long to match other SMP message functions.
bsp/sparc: Flush icache before first time enabling interrupts

A secondary processor might miss changes done to the trap table
if the instruction cache is not flushed. Once interrupts are enabled
any other required cache flushes can be ordered via the cache
manager.
score/sparc: Add comment on icache flush after trap table update

Changes to the trap table might be missed by other cores.
If the system state is up, the other cores can be notified
using SMP messages that they need to flush their icache.
If the up state has not been reached there is no need to
notify other cores. They will do an automatic flush of the
icache just after entering the up state, but before enabling
interrupts. Cache invalidation is required for both single
and multiprocessor systems.
bsp/sparc: Flush only instruction cache

The flush instruction on LEON flushes both the data and the instruction
cache. Flushing of just the instruction cache can be done by setting
the "flush instruction cache" bit in the cache control register.
score: Add SMP support to the cache manager

Adds functions that allows the user to specify which cores that should
perform the cache operation. SMP messages are sent to all the specified
cores and the caller waits until all cores have acknowledged that they
have flushed their cache. If CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING is
defined the instruction cache invalidation function will perform the
operation on all cores using the previous method.
smptests/smpcache01: Test the SMP cache manager

Invokes SMP cache management routines under different scenarios.