increase the data size to 16
modified the order of passing args to match def of fifo_mem_generic
modified the _din, _dout, _addr_w variables
to dout_r, addr_w_r, and _din to din_r & din_x
This is the methon that XESS uses _x outside of the FSM
when assigning variables and _r outside of the FSM for reading
Now generates both VHDL & Verilog
Code now synthesizes okay