ARM: tegra: cardhu: add pm267 to kbc int keys

Bug 896071

Change-Id: I1bcd8069bfccdd80a1506e71bb9cc0353b9ea9a6

Conflicts:

	arch/arm/mach-tegra/board-cardhu-kbc.c

Change-Id: I29af7c5289ae06757eb9cffce3065db08b3e8d06
Reviewed-on: http://git-master/r/97734
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
spi: tegra: register interrupt as ONESHOT

The Tegra spi's engine is design as it generates interrupt
when any error occurs and it keep transferring data. It does
not stop the engine once error occurred and interrupt generated.
This may cause reentry of ISR as on error case, isr get called
where it clears interrupt and because it is still in progress,
it again interrupts and schedule the thread.
The second time scheduling of the isr/thread can cause the issue
in queue management and sw state.
So Making the interrupt as ONESHOT so that the interrupt will not
get schedule until the engine is reset in error case.

Change-Id: I96daaf50102aede93164c82b7f6da235d0a7fbfc
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/101547
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jui Chang Kuo <jckuo@nvidia.com>
Tested-by: Jui Chang Kuo <jckuo@nvidia.com>
i2c: tegra: Fix i2c unknown interrupt issue

writes to modules on APB bus may complete out-of-order. need
to guarantee that the write is completed by reading it back.

read I2C_INT_STATUS back right after writing the current int status
in the isr to make sure the clear operation of I2C_INT_STATUS is
done before the interrupt is re-enabled.
the same also done for DVC_STATUS.

bug 980763

Change-Id: I34f18804d530ccadf561fe1736552b6a4dd6e4ce
Signed-off-by: Ken Chang <kenc@nvidia.com>
Reviewed-on: http://git-master/r/101925
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
spi: tegra: correct directions when syncing buffer for device/dma.

The Tx buffer to be synced with the direction of DMA_TO_DEVICE and
Rx buffer should be synced with direction of DMA_FROM_DEVICE.

bug 959947

Change-Id: I490a93e05723e3114c8ae3c640bb7eff23bcc75d
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/103095
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
arm: tegra: nvmap: remove nvmap.h from mach-tegra/include.

It is moved to kernel/include.
Bug 854182

Change-Id: I3fb729c88e29a9f213656fbf20810c10dfd9d7a6
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/102727
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
ARM: tegra: cardhu: add initial A07 support

Bug 970890

Change-Id: I24c3b1e2c621afbb90ced552194403f147e20a6c
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/102984
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
ARM: tegra: pcie: Fix for second pcie port detection.

PCIE card on second port doesn't get detected if the first
port is empty. If the link for first port is reset and the
second port is queried for card, it doesn't get detected.

Fix for the issue is do not reset the link if the port is
not detected in third attempt.

bug 970206

Change-Id: I4e4d32c22697b817381834ac746417437016d7f3
Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-on: http://git-master/r/101986
(cherry picked from commit c085f6b1b3a77b7aae3b04e22c7a9bfed8517c1e)
Reviewed-on: http://git-master/r/103077
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
video: tegra: dc: recover underflow error

1. set UF_LINE_FLUSH to 0 by default.
2. if it gets 4 consecutive frames with underflows, enable UF_LINE_FLUSH to
get rid of underflow condition.

Signed-off-by: Jay Cheng <jacheng@nvidia.com>
Change-Id: I6d647d958484ee355809036bec7ca1b0c716017b
Reviewed-on: http://git-master/r/103227
Reviewed-by: Michael I Gold <gold@nvidia.com>
video: tegra: dc: recover underflow error

1. set UF_LINE_FLUSH to 0 by default.
2. if it gets 4 consecutive frames with underflows, enable UF_LINE_FLUSH to
get rid of underflow condition.

Signed-off-by: Jay Cheng <jacheng@nvidia.com>
Change-Id: I6d647d958484ee355809036bec7ca1b0c716017b
Reviewed-on: http://git-master/r/103227
Reviewed-by: Michael I Gold <gold@nvidia.com>
video: tegra: dc: Init hdmi's platform data and fb

1. Change hdmi platform data structure's xres and yres values.
   These values were made same as LVDS panel (1366x768). LVDS
   runs fix display mode,but HDMI can switch to different modes.
   The new values (640x480) are corresponding to HDMI's fallback
   mode resolution.

2. Map bootloader's framebuffer content to fb1 also, to
   initialize fb1's content, and to avoid black & white
   strips when hdmi gets enabled but has no content in fb.

It sometimes causes inconsistency on fb_console mapped on HDMI.

Bug: 930136
Change-Id: Iecf0d8c1cdd6a1baec2aec9c5dded3d73d1347e1
Signed-off-by: Shashank Sharma <shashanks@nvidia.com>
Reviewed-on: http://git-master/r/103381
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
arm: tegra: thermal: removed TEGRA_THERMAL_SYSFS

Removed the CONFIG_TEGRA_THERMAL_SYSFS option. Any
throttling activities must go through the Linux
thermal sysfs framework now via CONFIG_THERMAL.

Change-Id: Ibe680d82d3225994e6bebcfe75a0f058e567e35c
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/103182
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
video: tegra: dc: Change the definitions in display feature table.

Change-Id: I13f0f7502aea7f43b2ddff12e9664c22a1d9bd21
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/103210
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
power: smb349: support for self-powered devices

Some self-powered devices doesn't strictly follow USB spec that
has 5V Vbus to upstream cannot work with mux on the data lines.

The MAX4983 mux routes the data lines to SMB349 rather than the
Tegra chip when PGOOD polarity is low-active and DCIN is 5V.

Change PGOOD not to invert polarity for the devices that has 5V to
upstream.

Bug 981761

Change-Id: Ic67ec66ce8936d9a9d5d2df7bca2ff7f9c65b147
Signed-off-by: Chandler Zhang <chazhang@nvidia.com>
Reviewed-on: http://git-master/r/103526
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
ARM: tegra: cardhu: add A07 memory table

Bug 970890

Change-Id: If0ebb1ad76dfe3267bc0acd3feae70a701c1dfdb
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/103237
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
ARM: Tegra: P1852: changed nor timing regs  and freq

Nor frequency and timing registers changed as per
values provided by syseng

Bug 978870

Change-Id: I18313c7df6265ddd4140d264ac2751ed8f1982df
Reviewed-on: http://git-master/r/103355
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Mohit Kataria <mkataria@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
ARM: tegra: decouple mode from flags

When doing LP2 on last standing CPU, we currently pass
"mode | flag" to a few functions as argument, with the
assumption that "mode" will be confined to lower 22 bits
in PMC_CTRL register and "flags" will occupy higher 10
bits. If "flags" grows downward or "mode" grows upward,
without this explicit knowledge, LP2 will break on the
last standing CPU. Therefore we need to decouple them.

Currently only "flags" part is being used when passed to
other subroutines, so use "flags" only.

Change-Id: I299c998145d81c17760bda8a0b56311fed553958
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/100358
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
arm: tegra: governor:  change governor using cpufreq interface

Older code sets "conservative" governor in early-suspend
using sysfs entries.This implementation changes governor
in early-suspend using cpufreq interfaces.

bug 871958

Change-Id: I721afb6184982a063dc5f330da31f8fb88481cfd
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: http://git-master/r/100849
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Revert "ARM: vfp: Prevent process migration"

This reverts commit 68667feb8eae225f1293a7044c989ab0bba8dbd1.

Change-Id: I59023f2d83392465f7a989693b67cef96d565ed9
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/102314
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
ARM: vfp: ensure preemption is disabled when enabling VFP access

The vfp_enable function enables access to the VFP co-processor register
space (cp10 and cp11) on the current CPU and must be called with
preemption disabled. Unfortunately, the vfp_init late initcall does not
disable preemption and can lead to an oops during boot if thread
migration occurs at the wrong time and we end up attempting to access
the FPSID on a CPU with VFP access disabled.

This patch fixes the initcall to call vfp_enable from a non-preemptible
context on each CPU and adds a BUG_ON(preemptible) to ensure that any
similar problems are easily spotted in the future.

originally from
http://git.kernel.org/?p=linux/kernel/git/will/linux.git;a=commit;h=468c963e0210bf8108b17cf75066f25f39cabb56

Change-Id: I26fff8abe4c18bd3291613f70d0228aa2313811a
Reported-by: Hyungwoo Yang <hwoo.yang@gmail.com>
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Reviewed-on: http://git-master/r/102315
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
ARM: tegra: define/enable ARCH_HAS_SUSPEND_PAGETABLE

For Tegra, the CPU suspend code path installs its own 1:1 pagetable
setup once at init time. This pagetable is used by all CPUs doing
suspend/resume.

We want to use the common ARM code for CPU suspend/resume, but don't
want the MMU reenable code to patch the current pagetable as it's
shared (and could cause problems if the pagetable loads/stores were
were interleaved).

The installed pagetable already covers the cpu_resume_turn_mmu_on
VA, so we're able to just use the existing pagetable. This sets up
the CONFIG option to skip this part of the MMU reenable.

Bug 929856

Change-Id: Ibbac258122df6def7f7a2d511778a6f11d474938
Signed-off-by: Chris Johnson <cwj@nvidia.com>
Reviewed-on: http://git-master/r/92350
Reviewed-by: Sang-Hun Lee <sanlee@nvidia.com>
Tested-by: Sang-Hun Lee <sanlee@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Ahung Cheng <ahcheng@nvidia.com>
Tested-by: Ahung Cheng <ahcheng@nvidia.com>
Reviewed-on: http://git-master/r/103205
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>