gpu: ipu-v3: Add ipu_idmac_enable_watermark()

Adds the function ipu_idmac_enable_watermark(), which enables or disables
watermarking in the IDMAC channel. Enabling watermarking can increase a
channel's AXI bus arbitration priority.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
gpu: ipu-v3: Add ipu_idmac_lock_enable()

Adds ipu_idmac_lock_enable(), which enables or disables channel
burst locking.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
gpu: ipu-cpmem: Add ipu_cpmem_set_block_mode()

Adds ipu_cpmem_set_block_mode().

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
gpu: ipu-cpmem: Add ipu_cpmem_set_axi_id()

Adds ipu_cpmem_set_axi_id() to set which AXI bus master the channel
will use to transfer data onto AXI bus.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
gpu: ipu-cpmem: Add ipu_cpmem_set_rotation()

Adds ipu_cpmem_set_rotation().

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
gpu: ipu-cpmem: Add second buffer support to ipu_cpmem_set_image()

Add a second buffer physaddr to struct ipu_image, for double-buffering
support.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
gpu: ipu-cpmem: Add ipu_cpmem_set_uv_offset()

Adds ipu_cpmem_set_uv_offset(), to set planar U/V offsets.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
gpu: ipu-v3: Add more planar formats support

Adds support for the following planar and partial-planar formats:

YUV422
NV12
NV16

Signed-off-by: Dmitry Eremin-Solenikov <dmitry_eremin@mentor.com>
Signed-off-by: Mohsin Kazmi <mohsin_kazmi@mentor.com>
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>

Unified base offset and Y plane offset into a single variable,
moved all ipu_cpmem_set_buffer calls to a single location.
Removed NV21 and NV61 for now. The IDMAC doesn't understand U/V
order for chroma interleaved formats, so we'd need to work around
this by implenting U/V switching via the CSC unit.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
gpu: ipu-cpmem: Add ipu_cpmem_dump()

Adds ipu_cpmem_dump() which dumps a channel's cpmem to debug.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
gpu: ipu-v3: Add ipu_dump()

Adds ipu_dump() which dumps IPU register state to debug.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
ARM: dts: imx6qdl: Add ipu aliases

Add ipu0 (and ipu1 for quad) aliases to ipu1/ipu2 nodes respectively.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
gpu: ipu-v3: Add ipu_get_num()

Adds of-alias id to ipu_soc and retrieve with ipu_get_num().

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
gpu: ipu-v3: Add IDMA channel linking support

Adds functions to link and unlink IDMAC source channels to sink
channels.

So far the following links are supported:

IPUV3_CHANNEL_IC_PRP_ENC_MEM -> IPUV3_CHANNEL_MEM_ROT_ENC
PUV3_CHANNEL_IC_PRP_VF_MEM   -> IPUV3_CHANNEL_MEM_ROT_VF
IPUV3_CHANNEL_IC_PP_MEM      -> IPUV3_CHANNEL_MEM_ROT_PP

More links can be added to the idmac_link_info[] array.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
gpu: ipu-v3: Add ipu_set_vdi_src_mux()

Adds ipu_set_vdi_src_mux() that selects the VDIC input (from CSI or memory).

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
gpu: ipu-v3: Add VDI input IDMAC channels

Adds the VDIC field input IDMAC channels. These channels
transfer fields F(n-1), F(n), and F(N+1) from memory to
the VDIC (channels 8, 9, 10 respectively).

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
ARM: dts: imx6qdl: Flesh out MIPI CSI2 receiver node

Add mode device info to the MIPI CSI2 receiver node: compatible string,
interrupt sources, clocks.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
ARM: imx6q: clk: Add video 27m clock

Adds a 27MHz clock that is a fixed /20 from the pll3_pfd1_540m clock.
The MIPI CSI2 receiver requires this clock.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
ARM: dts: imx: sabrelite: add video capture ports and endpoints

Defines the host v4l2-capture device node and an OV5642 camera sensor
node on i2c2. The host capture device is a child of ipu1. An OV5642
parallel-bus endpoint is defined that connects to the host parallel-bus
endpoint on CSI0, using the OF graph bindings described in
Documentation/devicetree/bindings/media/video-interfaces.txt.

ote there is a pin conflict with GPIO6. This pin functions as a power
input pin to the OV5642, but ENET requires it to wake-up the ARM cores
on normal RX and TX packet done events (see 6261c4c8). So by default,
capture is disabled, enable by uncommenting __OV5642_CAPTURE__ macro.
Ethernet will still work just not quite as well.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
ARM: dts: imx6-sabresd: add video capture ports and endpoints

Defines the host v4l2-capture device node and two camera sensors:
parallel-bus OV5642 and MIPI CSI-2 OV5640. The host capture device
is a child of ipu1. The MIPI CSI-2 receiver device is also defined.

The OV5642 is connected to the host parallel-bus endpoint on CSI0,
and the OV5640 is connected to the host MIPI CSI-2 endpoint on CSI1,
over virtual channel 0.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
ARM: dts: imx6-sabreauto: add video capture ports and endpoints

Defines the host v4l2-capture device node and the ADV7180 decoder
sensor. The host capture device is a child of ipu1. The ADV7180 is
connected to the host parallel-bus endpoint on CSI0.

On the sabreauto, two analog video inputs are routed to the ADV7180,
composite on Ain1, and composite on Ain3. Those inputs are defined
via inputs and input-names under the host endpoint node on CSI0.

Regulators and port expanders are defined which are required for the
ADV7180 (power pin is via port expander gpio on i2c3). The reset pin
to the port expander chip (MAX7310) is controlled by a gpio, so define
the reset-gpios property to control it.

The sabreauto uses a steering pin to select between the SDA signal on
i2c3 bus, and a data-in pin for an SPI NOR chip. Use i2cmux to control
this steering pin. Idle state of the i2cmux selects SPI NOR. This is not
a classic way to use i2cmux, since one side of the mux selects something
other than an i2c bus, but it works and is probably the cleanest
solution. Note that if one thread is attempting to access SPI NOR while
another thread is accessing i2c3, the SPI NOR access will fail since the
i2cmux has selected the SDA pin rather than SPI NOR data-in. This couldn't
be avoided in any case, the board is not designed to allow concurrent
i2c3 and SPI NOR functions (and the default device-tree does not enable
SPI NOR anyway).

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>