Add support for AXI4 and AXI4-Lite type busses

This commit introduces convertion between a foreign bus architecture and
Wishbone. By specifying "bustype=axi4" or "bustype=axi4-lite" on either
a slave or a master the interconnect will embed convertion cores and
change the output wires to be those of AXI4 / AXI4-Lite.

This is compatible with the "datawidth" directive.
Added Avalon support to wb_intercon_gen

Refactored code and introduced 'bustype=avalon' as well.

Bonus commit: Added clk/rst to bus converter logics.
Update wb_avalon_bridge for wb_intercon_gen

Renames port on wb_avalon_bridge to match those generated in
wb_intercon_gen. This also changes the view of the port to be an "input
master" to a "slave" port, which is functionally equivalent.
Disabled axi4 and axi4-lite bus types for now

The bus converter cores are not yet available, disable the bus types for
now to not confuse users. It is easy enough to enable by hand if you
really need it now.
Fail with exit code 1 if an Error is raised

Also, it is nicer to display the message to the user than
a full stack trace.