ARM64: add support for cache management instructions (VEX side):
  dc cvau, regX
  ic ivau, regX
  mrs regX, ctr_el0
Fixes #333228 and #333230.



git-svn-id: svn://svn.valgrind.org/vex/trunk@2851 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Renaming only (no functional change): rename IR artefacts to do 
with i-cache invalidation to be more consistent with new d-cache
invalidation functionality:
  Ijk_TInval          -> Ijk_InvalICache
  TISTART             -> CMSTART (CM == "Cache Management")
  TILEN               -> CMLEN
  VEX_TRC_JMP_TINVAL  -> VEX_TRC_JMP_INVALICACHE



git-svn-id: svn://svn.valgrind.org/vex/trunk@2852 8f6e269a-dfd6-0310-a8e1-e2731360e62c