x86: Simplify IPI processing with logical APIC IDs

We now have ffsl available, so we can avoid inverting the mask and
looking for zero bits.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
x86: Clear APIC on every SIPI event

The current logic only ensures that we clear the APIC when the CPU
enters the virtual wait-for-SIPI state. However, this does not cover the
case when we transfer a CPU from the root to a non-root cell. We only
stop the CPU for this, and reset it directly via a pseudo SIPI. This
change moves the clearing to the point where we are about to deliver the
SIPI.

The change has the positive side effect of moving potentially costly
APIC clearing out of the control_lock.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
x86: Fix argument widths of hypercall ABI

The x86 hypercall ABI defined 64-bit arguments and return codes so far.
However, our interface header took and returned only 32 bits. This
slipped through unnoticed because usually no physical addresses beyond
4G are passed to the Cell Create hypercall, the only place where it
practically matters.

Fix the issue and extend the ABI to support also 32-bit callers. We
define hypercall code and return value to be 32 bits, argument width are
now corresponding the the callers mode: 64 bits in IA-32e mode, 32 bits
otherwise. While the root cell still has to be in 64-bit mode, non-root
cells in other modes are now fine to invoke the hypercalls as well.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
x86: Fix name of sib.base

It's called "base" in the spec.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
x86: Add support for REX.B to MMIO instruction parser

In none of the supported modes, REX.B is relevant for us because we
obtain the memory address - which it influences by selecting the address
register - differently. Therefore, we can ignore this bit, extending the
set of supported MMIO instructions.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>