Implement LT opcode
Implement MOV instruction

Here's another loss of reversibility: MOV is just an OR.
Implement OR opcode
Implement SUB opcode
Fix VCD dump nested signal naming problem

I wasn't stripping the early components of the path correctly in VCD
dumps.  This means I was generating

  module A
    module A::B
      wire c

for the Chisel wire

  A::B::c

which is wrong.  This now generates

  module A
    module ;B
      wire c

which is the correct hierarchy.

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