hdl/modules/*/wb_acq_core/*: fix unsafe start pulse

The start acquisition pulse was not safe in all use
cases. Worse yet, due to recent changes the packet size
signal was being sampled in the wrong clock cycle and
producing incorrect results. Now, employing a feedback
pulse transfer between clock domains, we should be safer.

Also, added some debug signals and undocumented fields in
the wishbone status register (for debugging purposes).
hdl/modules/*/wb_fmc130m_4ch/*: output only 1x clock cycle.

Fow now, our design will run with 1x clock cycle due to
synthesis issues.
hdl/modules/pcie/common/*: fix almost full/empty threslhold

Native FIFOS must have a minimum "almost empty" threshold of 4.
Also, the "almost full" threshold must not be greater than size-4.