[sma_corr] Re-pipelined the xeng interleaving mux.

It used to be a latency=4 mux but the internal mux delay has been decreased
to 2 with a latency=2 pipeline added to all input ports. Syncs and other related signals
have also been properly accounted for (I think....)
Revert "[sma_corr] Re-pipelined the xeng interleaving mux."

This reverts commit d87b5460dd984fdcdff05081d1bd1df2f338783d.
[sma_corr] In xengx8/interleave, replaced BRAM-based ddelay1 with FF/SRL-based delay.
Revert "[sma_corr] In xengx8/interleave, replaced BRAM-based ddelay1 with FF/SRL-based delay."

This reverts commit 89ca59e9fe6911a48236f13217847abc1fe9fcd7.
[sma_corr] Decreased x_eng/../interleave BRAM delays by 1 (from 4 to 3).
Revert "[sma_corr] Decreased x_eng/../interleave BRAM delays by 1 (from 4 to 3)."

This reverts commit 193ef7dd6e28aa496f275646cdd6a9f8cf7d491d.
[sma_corr] Increased BRAM delay for x_eng/../interleave by 1 (from 4 to 5).
Revert "[sma_corr] Increased BRAM delay for x_eng/../interleave by 1 (from 4 to 5)."

This reverts commit 9237b9f0bc798944a3c5e39d0abcee2ae66d2678.
[sma_corr] Re-arranged QDRs again, 0/3 for accumulators with 1/2 for transposes.
[sma_corr] Swapped QDRs 0 and 3.
Revert "[sma_corr] Swapped QDRs 0 and 3."

This reverts commit e3dbfbe4494a96ea4520c5a05ac126a6b1dbe699.
[sma_corr] Swapped QDRs 1 and 2.
Revert "[sma_corr] Swapped QDRs 1 and 2."

This reverts commit 43d2d08ce656dbc9e70316a0742ae668e4edac4e.
Revert "[sma_corr] Re-arranged QDRs again, 0/3 for accumulators with 1/2 for transposes."

This reverts commit ad4c9390c81da1d69368b6eaa0a7391d8d11a49c.
[sma_corr] Added some pipeline delays before the visibs/del block.
Revert "[sma_corr] Added some pipeline delays before the visibs/del block."

This reverts commit 5c77377bcf9045a0a9b2ee714b28c35577755192.
[sma_corr] Replaced Xilinx delay blocks in sync/ with pipelines.
Revert "[sma_corr] Replaced Xilinx delay blocks in sync/ with pipelines."

This reverts commit 5027d99428cb6fdf96a5ed81681c3f8526458642.