msm: acpuclock-8974: Add support for 8974v3 speed bin

Add v3 frequency and voltage data corresponding to the voltage plan
for bringup.

Change-Id: I02f8885a5bc7798c5cfcae34cf952675f346b208
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
msm: acpuclock-8974: Apply 8974Pro bringup workaround

Fix soc version detection for 8974Pro and force 8974ab to use bringup
voltage plan.

Change-Id: I84bc7bf0912223b3826b8420c19c9e93e6a9f816
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
msm: acpuclk-8974: Update voltage tables for Pro variants

Hardware characterization provided updated voltages tables for 8974Pro.
Update acpuclock tables to match latest voltage plan.

Change-Id: Ie5abe6385446ed94147fbff6d910b9fd383327aa
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
Revert "msm: acpuclk-8974: Update voltage tables for Pro variants"

This reverts commit 05c31368cfe462809da462b36d6591d1e859f9b6.

We are observing a bunch of reports of L1 Parity Errors on 8974 Pro
variants. Raise voltages back to their original values to rule out
undervolting problems.

Change-Id: I64b84115dc73235f2819f3d46e14e40a93f6bfa4
Signed-off-by: Syed Rameez Mustafa <rameezmustafa@codeaurora.org>
msm: acpuclk-8974: Update voltage tables for Pro variants

Hardware characterization provided updated voltages tables for 8974Pro.
Update acpuclock tables to match latest voltage plan.

Change-Id: I7993717e7bbbc996f24678fc15fe65da590e7af5
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
msm: acpuclock-krait: Make changes to the PVS bin format

Add support for a new 4-bit PVS bin format; read the PVS
revision register in order to differentiate formats, and
update masks and shifts used when reading the PVS and
redundant selection bits.

Change-Id: I36ecc0aad212e16c157d27a5c7bc15b7ec560bf0
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
msm: acpuclock-8974: Update PVS table to match new voltage plan

Voltage plan has been updated for 8974Pro. Update PVS tables to match
the latest voltage plan.

Change-Id: Ide33874685755e76efcf8826e6946a11235b8e67
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
msm: acpuclock-8974: Update PVS table for msm8974 Pro

Update PVS table to match the latest voltage plan for msm8974 Pro.

Change-Id: Ieaba3a9b0108f00563c527b4b401a05deae74ec5
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
msm: acpuclock-8974: Remove unused 8974v1-specific data and code

General support for 8974v1 hardware was dropped long ago since this
early version of hardware was never commercialized. Clean up the
acpuclock driver by removing v1-specific code and data.

Change-Id: I79b33718a7df8ab832fa149d80511ea7d8cf562c
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
msm: clock-krait-8974: Add support for 8974 Krait clocks

The clock-krait-8974 driver uses the clock-krait library and models the
krait clock tree in MSM8974. The following data are read from device tree
the keep the driver more reusable:
- PVS tables for the CPUs and the L2 voltage table
- AVS configuration table
- HFPLL and efuse register bases
- Regulators used by the krait subsystem

Change-Id: I7b145c7f2361d93adbfbc2896040a19bf3be31a2
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
msm: clock-krait: Clock ops library for Krait subsystem clocks

The Krait subsystem has its own clock tree. Implement a clock-krait library
that provides a set of clock ops that model all the clock components
present in the Krait subsystem clock tree.

Change-Id: I41bb4243c28cd666ebe8e7c5a814c85401d92308
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
msm: clock-krait: Fix register checking for div clock

Fix the wrong operand used to mask divider bits.

Change-Id: If2be61dece01b8171b31938b3d7c14fb497c0fd3
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
msm: clock-krait-8974: Run force reinit sequence for all CPUs

The HFPLL and krait mux force reinit sequence needs to be run for all CPUs
irrespective of whether they are online or offline. This is necessary to
ensure that when offline CPUs are brought online later on, they are brought
up at a known frequency.

To be able to do the above, we also have to remove the prepare count check
in krait core clock set rate ops. It's safe to do so since that check
wasn't really providing any additional protection on top of the checks
already done in the cpufreq driver.

Change-Id: Ia73459ee03d339c948d7f2ea9516df1c0d9b8bd0
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
msm: clock-krait: Always configure low performance level krait clock tree

With newer HW versions, switching between BHS and LDO power supplies also
switches the CPU between the high performance clock tree output and low
performance clock tree output respectively.

Since the low performance clock tree is never configured (since it was
never used before), with newer HW versions running the CPU off the LDO
supply would also run the CPU at an unknown frequency that could be higher
that the max frequency for that specific voltage/current level.

Fix this by always configuring the high performance clock tree and the low
performance clock tree to the same frequency. This change is also
compatible with HW versions that don't have a low performance clock tree
since the register bits that correspond to the low performance clock tree
are marked as unused/reserved.

Change-Id: Ie82bf735220619be7ffd496cbd8b017c89904b41
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
msm: clock-krait: Read CONFIG_CTL value and the vco mask from DT

The config control register may have different reset
values on different MSMs. Also, not all HFPLLS may need
to switch between VCO modes. Read both the config control
register initialization value and the VCO user control
mask from device tree.

Change-Id: I832ee3acaa7f4b7b0637d0732ddf275d9475e8bc
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
msm: acpuclock: Delete legacy acpuclock-krait drivers

The acpuclock-krait driver and the corresponding chip specific files have
been replaced with the clock-krait and clock-krait-8974 driver and
corresponding DT nodes. So, delete the unused files.

Change-Id: I193f0ae37940b537dec4fdfc2a3638d8cb0bcf0a
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>