Fix all the current issues with the AArch64 register cache.
Fixes all the current issues I've been experiencing.
Scaled back the register cache idea for now so I can actually work on some real instructions.

Tested this work with unit tests so I know it works.
Unit tests are pretty great things.
JIT: optimize andi(s)_rc

We usually don't need to do a sign-extend for the resulting flags.
JIT: save an instruction in psq_l
Merge pull request #1065 from Sonicadvance1/AArch64-fix-regcache

Fix all the current issues with the AArch64 register cache.
Merge pull request #1077 from FioraAeterna/integeropts2

Two small JIT optimizations
Revert "Two small JIT optimizations"
Merge pull request #1088 from FioraAeterna/revert-1077-integeropts2

Revert "Two small JIT optimizations"
x64Emitter: fix silent failure if WriteNormalOp is passed two memory operands

Should now fail loudly and clearly instead.
JIT: support immediate stores
Merge pull request #1089 from FioraAeterna/fixemittersilentfail

x64Emitter: fix silent failure if WriteNormalOp is passed two memory operands
GekkoDisassembler: fix/improve disassembly for a few instructions
Merge pull request #1091 from FioraAeterna/fixdisasm

GekkoDisassembler: fix/improve disassembly for a few instructions
Merge pull request #805 from FioraAeterna/storerefactor

JIT: support immediate stores
Fix missing "return"
Merge pull request #1092 from comex/that-aint-ruby

Fix missing "return"
Reorganize carry to store flags separately instead of part of XER

Also correct behavior with regards to which bits in XER are treated as zero
based on a hwtest (probably doesn't affect any real games, but might as well
be correct).
JIT: generic branch merging

Why merge just cmps and rlwinm when we can merge ALL the branches?