clk: sunxi: Add support for USB clock-register reset bits

The usb-clk register is special in that it not only contains clk gate bits,
but also has a few reset bits. This commit adds support for this by allowing
gates type sunxi clks to also register a reset controller.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
clk: sunxi: Add USB clock register defintions

Add register definitions for the usb-clk register found on sun4i, sun5i and
sun7i SoCs.

Signed-off-by: Roman Byshko <rbyshko@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sun4i: dt: Add bindings for USB clocks

Signed-off-by: Roman Byshko <rbyshko@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sun5i: dt: Add bindings for USB clocks

Signed-off-by: Roman Byshko <rbyshko@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sun7i: dt: Add bindings for USB clocks

Signed-off-by: Roman Byshko <rbyshko@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
net: rfkill: gpio: fix gpio name buffer size off by 1

snprintf should be passed the complete size of the buffer, including
the space for '\0'. The previous code resulted in the *_reset and
*_shutdown strings being truncated.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
net: rfkill: gpio: use clk_prepare_enable/clk_disable_unprepare

rfkill-gpio calls clk_enable() without first calling clk_prepare(),
resulting in a warning and no effect. Switch to clk_prepare_enable()
and clk_disable_unprepare.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
net: rfkill: gpio: fix reversed clock enable state

rfkill-gpio has clk_enabled = blocked, which is true when rfkill
blocks the device. This results in calling clock enable/disable at
the wrong time. Reversing the value fixes this.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
net: rfkill: gpio: add device tree support

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
net: rfkill: gpio: add clock-frequency device tree property

Some devices, such as Broadcom Bluetooth devices, require a specific
clock rate for the clock tied to the rfkill device. Add clock-frequency
property so we can specify this from the device tree.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
pinctrl: sunxi: create irq/pin mapping during init

The irq/pin mapping is used to lookup the pin to mux to the irq
function when the irq is enabled. It is created when gpio_to_irq
is called. Creating the mapping during init allows us to map the
interrupts directly from the device tree.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
pinctrl: sunxi: add IRQCHIP_SKIP_SET_WAKE flag for pinctrl irq chip

The sunxi pinctrl irq chip driver does not support wakeup at the
moment. Adding IRQCHIP_SKIP_SET_WAKE lets the irqs work with drivers
using wakeup.

Also add a name to the irq chip.
ARM: dts: sun7i: Add #interrupt-cells to pinctrl node

The pinctrl device is also an interrupt controller for external
interrupts. Add the missing #interrupt-cells property.

Also remove the unused #address-cells property.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
ARM: dts: sun7i: add pin muxing options for UART2

UART2 is used on CubieTruck to connect to the Bluetooth module.
Add the pin set used in this case.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
ARM: dts: sun7i: add WiFi module to Cubietruck DTS

The CubieTruck has an AMPAK AP6210 WiFi+Bluetooth module. The WiFi
part is a BCM43362 IC connected to MMC2 in the A20 SoC via SDIO.
The IC also takes a 32.768 KHz low power clock input, and a power
enable signal via GPIO.

The WiFi module supports out-of-band interrupt signaling via GPIO,
but this is not supported in this patch.
ARM: dts: sun7i: add bluetooth module to CubieTruck DTS

The CubieTruck has an AMPAK AP6210 WiFi+Bluetooth module. The
Bluetooth part is a BCM20710 IC connected to UART2 in the A20
SoC. The IC also takes a 32.768 KHz low power clock input, a power
enable signal and a wake signal via GPIO.

The Bluetooth module supports out-of-band interrupt signaling via
GPIO, but this is not supported in this patch.
clk: sunxi: Add support for PLL6 on the A31

The A31 has a slightly different PLL6 clock. Add support for this new clock in
our driver.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: sun6i: dt: Add PLL6 and SPI module clocks

The module clocks in the A31 are still compatible with the A10 one. Add the SPI
module clocks and the PLL6 in the device tree to allow their use by the SPI
controllers.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
spi: sunxi: Add Allwinner A31 SPI controller driver

The Allwinner A31 has a new SPI controller IP compared to the older Allwinner
SoCs.

It supports DMA, but the driver only does PIO for now, and DMA will be
supported eventually.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: sun6i: dt: Add SPI controllers to the A31 DTSI

The A31 has 4 SPI controllers. Add them in the DTSI.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>