* loop-unroll.c (struct iv_to_split): Remove n_loc and loc fields.
	(analyze_iv_to_split_insn): Don't initialize them.
	(get_ivts_expr): Removed.
	(allocate_basic_variable, insert_base_initialization): Use
	SET_SRC instead of *get_ivts_expr.
	(split_iv): Use &SET_SRC instead of get_ivts_expr.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213621 138bc75d-0d04-0410-961f-82ee72b054a4
[gcc/]

	* graphite-isl-ast-to-gimple.c:
	(set_options): New function.
	(scop_to_isl_ast): Add calling of set_options.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213623 138bc75d-0d04-0410-961f-82ee72b054a4
[AArch64] Some aarch64-builtins.c cleanup.

gcc/

	* config/aarch64/aarch64-builtins.c
	(aarch64_simd_builtin_type_mode): Delete.
	(v8qi_UP): Remap to V8QImode.
	(v4hi_UP): Remap to V4HImode.
	(v2si_UP): Remap to V2SImode.
	(v2sf_UP): Remap to V2SFmode.
	(v1df_UP): Remap to V1DFmode.
	(di_UP): Remap to DImode.
	(df_UP): Remap to DFmode.
	(v16qi_UP):V16QImode.
	(v8hi_UP): Remap to V8HImode.
	(v4si_UP): Remap to V4SImode.
	(v4sf_UP): Remap to V4SFmode.
	(v2di_UP): Remap to V2DImode.
	(v2df_UP): Remap to V2DFmode.
	(ti_UP): Remap to TImode.
	(ei_UP): Remap to EImode.
	(oi_UP): Remap to OImode.
	(ci_UP): Map to CImode.
	(xi_UP): Remap to XImode.
	(si_UP): Remap to SImode.
	(sf_UP): Remap to SFmode.
	(hi_UP): Remap to HImode.
	(qi_UP): Remap to QImode.
	(aarch64_simd_builtin_datum): Make mode a machine_mode.
	(VAR1): Build builtin name.
	(aarch64_init_simd_builtins): Remove dead code.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213627 138bc75d-0d04-0410-961f-82ee72b054a4
[convert.c] PR 61876: Guard transformation to lrint by -fno-math-errno.

	* convert.c (convert_to_integer): Guard transformation to lrint by
	-fno-math-errno.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213628 138bc75d-0d04-0410-961f-82ee72b054a4
Correct usage of dg-require-fork in gcc.dg/torture/ftrapv-1.c

	* gcc.dg/torture/ftrapv-1.c: Correct usage of dg-require-fork.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213629 138bc75d-0d04-0410-961f-82ee72b054a4
[ARM] Adjust clz, rbit and rev patterns for -mrestrict-it.

	* config/arm/arm.md (clzsi2): Set predicable_short_it attr to no.
	(rbitsi2): Likewise.
	(*arm_rev): Set predicable and predicable_short_it attributes.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213630 138bc75d-0d04-0410-961f-82ee72b054a4
[ARM/AArch64] Add CRC32 scheduling information to Cortex-A53 and Cortex-A57.

	* config/arm/cortex-a15.md (cortex_a15_alu_shift): Add crc type
	to reservation.
	* config/arm/cortex-a53.md (cortex_a53_alu_shift): Likewise.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213632 138bc75d-0d04-0410-961f-82ee72b054a4
[AArch64] Implement some vmul*_lane*_f* intrinsics in arm_neon.h.

	* config/aarch64/arm_neon.h (vmul_f64): New intrinsic.
	(vmuld_laneq_f64): Likewise.
	(vmuls_laneq_f32): Likewise.
	(vmul_n_f64): Likewise.
	(vmuld_lane_f64): Reimplement in C.
	(vmuls_lane_f32): Likewise.

	* gcc.target/aarch64/simd/vmul_f64_1.c: New test.
	* gcc.target/aarch64/simd/vmul_n_f64_1.c: Likewise.
	* gcc.target/aarch64/simd/vmuld_lane_f64_1.c: Likewise.
	* gcc.target/aarch64/simd/vmuld_laneq_f64_1.c: Likewise.
	* gcc.target/aarch64/simd/vmuls_lane_f32_1.c: Likewise.
	* gcc.target/aarch64/simd/vmuls_laneq_f32_1.c: Likewise.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213634 138bc75d-0d04-0410-961f-82ee72b054a4
[AArch64] Implement some saturating math NEON intrinsics.

	* config/aarch64/aarch64-simd.md (aarch64_sqdmulh_laneq<mode>):
	Use VSDQ_HSI mode iterator.
	(aarch64_sqrdmulh_laneq<mode>): Likewise.
	(aarch64_sq<r>dmulh_laneq<mode>_internal): New define_insn.
	* config/aarch64/aarch64-simd-builtins.def (sqdmulh_laneq):
	Use BUILTIN_VDQHS macro.
	(sqrdmulh_laneq): Likewise.
	* config/aarch64/arm_neon.h (vqdmlalh_laneq_s16): New intrinsic.
	(vqdmlals_laneq_s32): Likewise.
	(vqdmlslh_laneq_s16): Likewise.
	(vqdmlsls_laneq_s32): Likewise.
	(vqdmulhh_laneq_s16): Likewise.
	(vqdmulhs_laneq_s32): Likewise.
	(vqrdmulhh_laneq_s16): Likewise.
	(vqrdmulhs_laneq_s32): Likewise.

	* gcc.target/aarch64/simd/vqdmlalh_laneq_s16_1.c: New test.
	* gcc.target/aarch64/simd/vqdmlals_laneq_s32_1.c: Likewise.
	* gcc.target/aarch64/simd/vqdmlslh_laneq_s16_1.c: Likewise.
	* gcc.target/aarch64/simd/vqdmlsls_laneq_s32_1.c: Likewise.
	* gcc.target/aarch64/simd/vqdmulhh_laneq_s16_1.c: Likewise.
	* gcc.target/aarch64/simd/vqdmulhs_laneq_s32_1.c: Likewise.
	* gcc.target/aarch64/simd/vqrdmulhh_laneq_s16_1.c: Likewise.
	* gcc.target/aarch64/simd/vqrdmulhs_laneq_s32_1.c: Likewise.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213635 138bc75d-0d04-0410-961f-82ee72b054a4
[AArch64] Fix types for vqdmlals_lane_s32 and vqdmlsls_lane_s32 intrinsics.

	* config/aarch64/arm_neon.h (vqdmlals_lane_s32): Use scalar types
	rather than singleton vectors.
	(vqdmlsls_lane_s32): Likewise.

	* gcc.target/aarch64/scalar_intrinsics.c (test_vqdmlals_lane_s32):
	Fix types.
	(test_vqdmlsls_lane_s32): Likewise.
	* gcc.target/aarch64/simd/vqdmlals_lane_s32.c: Likewise.
	* gcc.target/aarch64/simd/vqdmlsls_lane_s32.c: Likewise.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213636 138bc75d-0d04-0410-961f-82ee72b054a4
2014-08-05  Richard Biener  <rguenther@suse.de>

	PR rtl-optimization/61672
	* emit-rtl.h (mem_attrs_eq_p): Declare.
	* emit-rtl.c (mem_attrs_eq_p): Export.  Handle NULL mem-attrs.
	* cse.c (exp_equiv_p): Use mem_attrs_eq_p.
	* cfgcleanup.c (merge_memattrs): Likewise.
	Include emit-rtl.h.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213638 138bc75d-0d04-0410-961f-82ee72b054a4
Fixed text formatting


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213640 138bc75d-0d04-0410-961f-82ee72b054a4
	Implement constexpr variable templates
	* decl.c (grokvardecl): Handle specializations of variable templates.
	(grokdeclarator): Handle variable template id expressions and NULL_TREE
	return from grokvardecl.
	* decl2.c (check_member_template): Allow declaration of template member
	variables.
	* parser.c (cp_parser_template_id): Build a TEMPLATE_ID_EXPR for
	variable templates.
	* pt.c (check_template_variable): Accept variable temploids at
	non-class scope.
	(push_template_decl_real): The current instantiation of a template
	can be a VAR_DECL.
	(determine_specialization): Accept variable templates.
	(check_explicit_specialization): Handle and check for malformed
	variable template specializations.
	(lookup_template_variable): New.
	(tsubst_decl): Handle variable template specializations.
	(do_decl_instantiation): Handle template variables.
	(instantiate_decl): Handle template variables.
	* semantics.c (finish_template_variable): New.
	(finish_id_expression): Instantiate variable templates.
	* cp-tree.h (variable_template_p): New.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213641 138bc75d-0d04-0410-961f-82ee72b054a4
Fix typos.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213642 138bc75d-0d04-0410-961f-82ee72b054a4
Fix more typos.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213643 138bc75d-0d04-0410-961f-82ee72b054a4
fix pr62009 use after free in redirect_edge_var_map_dup

The change to get the entry for the old edge before inserting the new
one was incorrect because if inserting the new one resized the table
then the pointer to the entry for the old one would become invalid.

gcc/

	* tree-ssa.c (redirect_edge_var_map_dup): insert newe before
	getting olde.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213644 138bc75d-0d04-0410-961f-82ee72b054a4
gdbhooks.py: add "break-on-pass" command

gcc/
2014-08-05  David Malcolm  <dmalcolm@redhat.com>

        * gdbhooks.py (find_gcc_source_dir): New helper function.
        (class PassNames): New class, locating and parsing passes.def.
        (class BreakOnPass): New command "break-on-pass".



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213646 138bc75d-0d04-0410-961f-82ee72b054a4
Daily bump.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213649 138bc75d-0d04-0410-961f-82ee72b054a4
[Patch, microblaze]: Add optimized lshrsi3

When barrel shifter is not present, the immediate value
is greater than #5 and optimization is -OS, the
compiler will generate shift operation using loop.

Changelog

2013-11-26  David Holsgrove <david.holsgrove@xilinx.com>

 * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn

ChangeLog/testsuite

2014-02-12  David Holsgrove <david.holsgrove@xilinx.com>

 * gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c: New test.

Signed-off-by:Nagaraju <nmekala@xilix.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, microblaze]: Add INIT_PRIORITY support

Added TARGET_ASM_CONSTRUCTOR and TARGET_ASM_DESTRUCTOR macros.

These macros allows users to control the order of initialization
of objects defined at namespace scope with the init_priority
attribute by specifying a relative priority, a constant integral
expression currently bounded between 101 and 65535 inclusive.

Lower numbers indicate a higher priority.

Changelog

2013-11-26  Nagaraju Mekala <nagaraju.mekala@xilinx.com>

 * gcc/config/microblaze/microblaze.c: Add microblaze_asm_constructor,
   microblaze_asm_destructor. Define TARGET_ASM_CONSTRUCTOR and
   TARGET_ASM_DESTRUCTOR.

Signed-off-by:nagaraju <nmekala@xilix.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>