msm: clock: Add pre_set_rate and post_set_rate ops

Some clocks might need to perform additional steps before/after a voltage
changes happen during a rate change. To accomodate such clocks and similar
requirements from new clock types in the future, add generic
pre/post_set_rate ops that are called before any HW state change is done
for set rate.

Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
msm: clock-8974: Add an active-only GPLL0 clock

The clock-krait driver will require an active-only GPLL0
clock to select as a source for the CPU clock(s). Add this
clock.

Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
msm: clock-dummy: Rate-setable independent dummy clocks

Previously dummy clocks share same underlying clk struct.  clk_get_rate()
always returns 0.  Add a new macro DEFINE_CLK_DUMMY to create different
dummy clocks.  These clocks remember last set rate and return it for
clk_get_rate().  This is necessary for fake clocks to return desired
rate in virtio.

For any dummy clock that might need to handle clk_get_rate(), the new
macro is recommended.

Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
msm: clock-8610: Switch camera muxes to generic mux implementation

The camera mux implementation used ops in clock-local2
written specifically for the 8610 camera mux clocks.
Switch to the more generic mux implementation in the
clock-generic library, and delete the 8610 specific
implementation.

Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
msm: clock-generic: Handle round rate return values greater than LONG_MAX

The return type of clk_round_rate() is long. So, technically it can return
only rates as large as LONG_MAX (~2.1 GHz). But CPU clocks can already go
past 2.1 GHz and any return value greater than LONG_MAX will appear as a
negative number to the caller.

So, make the clock-generic implementation a bit more selective/intelligent
about treating negative return values from clk_round_rate() as errors. If
the returned negative number is not one of the standard error values
(IS_ERR_VALUE), then treat the negative long number as an unsigned long
rate.

Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
msm: clock-generic: Make ops options for div_clk

Fixed divider clocks have no need for any clk_div_ops. So, make the entire
ops optional for div_clk. With this in mind, add more NULL pointer checks
for ops.

Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
msm: clock-generic: Fix race condition between mux set rate and en/dis

Some mux implementations might switch to/from a low power parent as part of
their disable/enable ops. This can race with the temporary switch to the
"safe parent" that's done during a mux set rate. So, grab the enable lock
while temporarily switching to the safe parent.

The onus of remembering the last requested set_mux_sel and setting it back
to that when the mux is enabled is still the responsibility of the specific
implementation.

Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
msm: clock-generic: Add support for recursive set parent to mux_clk

When there are a bunch of nested muxes and a consumer calls
clk_set_parent() on the top level mux, it's possible that the consumer
doesn't care if the new parent is an immediate parent to the top level mux
and just wants the output from the new parent. So, recursively search for
the new parent (if recursive set parent is enabled for the mux) and get the
output of the new parent even if it has to go through multiple levels of
consecutive muxes.

Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
msm: clock-generic: Refactor round rate code

Use helper APIs to simplify div_clk and mux_clk round rate code.

Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
msm: clock-generic: Update the rate field on mux parent change.

Changing the parent of a mux changes its rate to the rate of the new
parent.  So, update the rate field of the clock when changing the parent of
the clock.

Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
msm: clock-generic: Introduce an ext_clk clock type

Some clock controllers have input clock signals from
other clock controllers or hardware blocks. To model
these exterior signals, introduce an ext_clk type that
just passes requests to its parent clock. The clock
controller using the ext_clk type will have to do a
clk_get to get a handle to the external clock, and set
that as the parent on the ext_clk clock.

Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
msm: clock-krait: Clock ops library for Krait subsystem clocks

The Krait subsystem has its own clock tree. Implement a clock-krait library
that provides a set of clock ops that model all the clock components
present in the Krait subsystem clock tree.

Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
msm: clock-krait-8974: Add support for 8974 Krait clocks

The clock-krait-8974 driver uses the clock-krait library and models the
krait clock tree in MSM8974. The following data are read from device tree
the keep the driver more reusable:
- PVS tables for the CPUs and the L2 voltage table
- AVS configuration table
- HFPLL and efuse register bases
- Regulators used by the krait subsystem

Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
msm: clock-krait-8974: Run force reinit sequence for all CPUs

The HFPLL and krait mux force reinit sequence needs to be run for all CPUs
irrespective of whether they are online or offline. This is necessary to
ensure that when offline CPUs are brought online later on, they are brought
up at a known frequency.

To be able to do the above, we also have to remove the prepare count check
in krait core clock set rate ops. It's safe to do so since that check
wasn't really providing any additional protection on top of the checks
already done in the cpufreq driver.

Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
msm: clock-krait: Always configure low performance level krait clock tree

With newer HW versions, switching between BHS and LDO power supplies also
switches the CPU between the high performance clock tree output and low
performance clock tree output respectively.

Since the low performance clock tree is never configured (since it was
never used before), with newer HW versions running the CPU off the LDO
supply would also run the CPU at an unknown frequency that could be higher
that the max frequency for that specific voltage/current level.

Fix this by always configuring the high performance clock tree and the low
performance clock tree to the same frequency. This change is also
compatible with HW versions that don't have a low performance clock tree
since the register bits that correspond to the low performance clock tree
are marked as unused/reserved.

Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
msm: clock-krait: Read CONFIG_CTL value and the vco mask from DT

The config control register may have different reset
values on different MSMs. Also, not all HFPLLS may need
to switch between VCO modes. Read both the config control
register initialization value and the VCO user control
mask from device tree.

Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
clock-krait-8974: Increase PVS bin efuse field to a 4-bit field

This also needs changes to the redundant fuse data field to support making
corrections to a 4-bit field.

Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
msm: clock-krait-8974: Fall back to safest PVS when table not found

If there is new hardware that uses unexpected PVS/Speed bin bits, we
should fall back to the safest PVS table instead of failing to probe.
Implement this fall back during clock-krait-8974 probe.

Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
msm: clock-generic: Reorganize divider clock parameters

Move some common parameters used by the div_round_rate() into a new
struct. This will allow other clock types to reuse this function.

Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
msm: clock-generic: Return best parent_rate from div_round_rate

Returning only the rounded rate and corresponding divider is not
sufficient. Since these values must be represented as integers, rather
than fractions, their product may not be equal to the actual parent
clock rate necessary.

Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>