The msr instruction failed to change the nzcv register value correctly.

This bug resolves this bug by adding the decoding rule for handling nzcv
modifications.

[matz: Check for op1==3 as well]
tst instruction is correctly decoded but incorrectly handled when working in 32-bit regsize mode.

Only low 32 bits should be anded and referred for setting the n value in pstate.
Merge branch 'aarch64-1.6' of https://github.com/susematz/qemu into toupstream

Conflicts:
	target-arm/translate-a64.c