mmc: msm_sdcc: Vote for MSM bus clocks before enabling iface_clk

The current driver just enables "iface_clk" before accessing its
registers but MSM bus clocks are also required for register access
without which any register access would result in chip reset.

The MSM bus clocks can be enabled by setting vote to MSM bus bandwidth
driver. Currently, voting is being done in msmsdcc_enable/disable but these
functions will not be invoked by MMC core layer for some cases such
as mmc_power_up/mmc_power_off, which require peripheral register
access.

To resolve the above mentioned problem, bus voting and de-voting will
now be done as part of clocks management within the MSM SDCC driver.

Change-Id: I4ac514e7348a53ed2816eb4114aa17eba9cedf01
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
mmc: msm_sdcc: fix pwrsave bit handling

SDCC controller provides the PWRSAVE control bit to automatically
disable the clock to card when there is no activity with card.
SDCC driver provides the compile time option to disable this pwrsave
feature completely but some of the recent driver changes ignore this
and may enable the pwrsave feature even when its not required. This
change ensures that we always check if the pwrsave is allowed or not
before really enabling it.

CRs-Fixed: 490017
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
(cherry picked from commit 5e26b136842f196741b3d799da982e2ab23e764e)

Change-Id: I3d3629ec3bb8f3ddfcf0bd83423073c72252aa8c
Signed-off-by: Sridhar Nelloru <nellos@codeaurora.org>
msm_sdcc: remove 5-second mdelay on command timeout

Signed-off-by: Iliyan Malchev <malchev@google.com>
mmc: msm_sdcc: Reset interrupt MASK register (MCI_MASK0) on powering off

In one corner case, the SD card is stuck in a bad state with its DAT0
line pulled low, and SDCC is waiting on the interrupt when the line
goes back high. But due its bad state eventually the SD card is removed
from the system.

Later during re-scanning of the devices, the SD card is power-cycled and
added to the system. But now the pending interrupts for SD card is
received as the interrupt MASK register (MCI_MASK0) was not cleared.

To prevent such cases reset the interrupt MASK register (MCI_MASK0) while
powering off to prevent any pending interrupts after power-cycle.

CRs-Fixed: 396706
Change-Id: I83c087a76cd92f20c5990a787296e093a13478ad
Signed-off-by: Pratibhasagar V <pratibha@codeaurora.org>
mmc: msm_sdcc: prevent possible NULL pointer access

mmc_signal_sdio_irq() should only be called if SDIO interrupt is
received for SDIO card. If mmc_signal_sdio_irq() function is called
when card is not present or for non-SDIO card, it may result into
NULL pointer access (due to uninitialized spin lock access) inside
mmc_signal_sdio_irq() function.

This change fixes the above issue by adding relevant safety checks in
driver.

CRs-Fixed: 423795
Change-Id: I1829acd81f91b4d0e01d509dd9e0926547cec7a0
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>

Conflicts:
	drivers/mmc/host/msm_sdcc.c
drivers/mmc/msm_sdcc: code style
drivers/mmc/host/msm_sdcc: enable Runtime PM
 mmc: msm_sdcc: set DDR timing mode before setting the clock rate

Setting DDR timing mode in controller before setting the clock
rate will make sure that card don't see the double clock rate
even for very small amount duration. Some eMMC cards seems to lock
up if they see clock frequency > 52MHz.

Change-Id: I8105cf52c07df01d66c3e15304ea10e2cbc498ff
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
mmc: msm_sdcc: fix clock gating handling using pwrsave control bit

SDCC controller provides the PWRSAVE control bit to automatically
disable the clock to card when there is no activity with card. SDCC
host controller driver always enables this feature but few SDIO
cards may require the clocks to be always running (even during
inactivity period) to raise the interrupt notification to host so
for such cards, enabling PWRSAVE fature may cause functional failures.

This change checks whether it is ok to gate the card clock before
enabling the PWRSAVE feature.

Change-Id: If36a6a20d59aeb555ece2a6959ab5407f90c787c
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
mmc: msm_sdcc: enable asynchronous interrupt support in 4-bit mode

SDIO 3.0 specification has added the support for asynchronous interrupt
period during which card allows the clock to be gated off.

As SDCC driver is capable of handling the asynchronous interrupt, advertise
MMC_CAP2_ASYNC_SDIO_IRQ_4BIT_MODE capability.

CRs-Fixed: 490008
Change-Id: Ic292f379795a821a0aa678d439eac9c2e3e560b7
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
 mmc: msm_sdcc: add stop transmission support

Large packed write request may take pretty long time to complete
causing the next read operation (if any) to wait for current write
to complete.

Instead we should interrupt the current write operation and execute
waiting read operation and once the read is completed, go back to
interrupted write operation and resume it.

To support this functionality, we have added support for following 2
new host operations in our driver:
1. int (*stop_request)(struct mmc_host *host)
        => Call this op to stop the current transfer synchronously.
2. unsigned int (*get_xfer_remain)(struct mmc_host *host);
        => Call this function to get the remaining number of bytes
           for current transfer

Change-Id: Ic8876f33f07f08792765154a7dacb6a14508966f
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Signed-off-by: Maya Erez <merez@codeaurora.org>
Revert " mmc: msm_sdcc: add stop transmission support"

This reverts commit 2b6937cccb2ef6353fb3f1a1e63b14f56a80285d.
mmc: msm_sdcc: Poll hardware register with iopoll API

While polling a hardware register for a fixed period of time, a task
may be preempted, causing the total time elapsed to exceed the fixed
period. For more accurate accounting, several iterations of a timed
delay can be used, and guarantees that the register will be polled for
at least the specified period of time before a timeout error is
reported.

CRs-Fixed: 421219
Change-Id: I8bc7ddb0ec2cd18085c2ee666754febac9376cbb
Signed-off-by: Oluwafemi Adeyemi <aadeyemi@codeaurora.org>

Conflicts:
	drivers/mmc/host/msm_sdcc.c