rtl: make all vectors little endian.
rtl/cache: fix flush not writing final word.

For a line fill, we read the word from memory and write to the data ram
using the same offset and can start fetching from the next address.
When flushing we read from the data ram and write to the same offset,
and can pipeline the next data ram read.  The pipelining wasn't working
correctly and we could sometimes fail to write back the final word of a
line.
rtl/cache: remove duplicated logic.

Eviction/flush and write-miss/bypass have shared logic, make those into
common case statements.