Fix interpreter's implementations of mtfsfi, mtfsb0, and mtfsb1.

6xx_pem states that bits 1 and 2 of the FPSCR aren't set via mtfsfi.
With a hardware test this has been proven false, mtfsfi can set them to whatever it wants.

6xx_pem also states that bits 1 and 2 of the FPSCR can't be set via mtfsb0/1.
With a hardware test this has been proven to be true, these instructions can not set/clear these bits.

6xx_pem states that bit 20 is a reserved bit, that's all it says.
With a hardware test, this bit has been proven to only ever be zero and can't be set to anything else with any of these instructions.

Interpreter wrongly assumed that FEX will /always/ be zero, so it would set it to zero on a mffs instruction.
This has been rectified.
Should we perhaps set FX here too (or elsewhere)? According to the docs, any exception bit transitioning from 0 to 1 causes this to be set (except when done from mtfsfi and mtfsf).