List of files affected by the bouyer-ide branch. Please keep up-to-date !
Commit changes to the IDE system in a branch. This allows a better separation
between higth-level and low-level (i.e. registers read/write) and generalize
the queue for all commands. This also add supports for IDE DMA.
Patches from Leo Weppelman for IDE on atari, with minor fixes by me
(needed the addition of a void wdcrestart __P((void*)) function).
Quoting his words:
These diffs are preliminary because it looks like the free_hw() function
does not get called. This is only a problem on the atari falcon. I have not
yet been able to track this down.
Also, KNF wdc.c.
A few bux fixes (untested):
 - If the PIO mode of the controller is unknown, put the drive in the
   hightest mode it supports. A drive in a faster mode than the controller
   should work.
 - Create DMA maps even for unknown controllers in pciide.
Add a missing LIST_INIT().
- call wdc_ata_bio_done() only once.
- better error recovery: if an error occured, retry the transfer in
  single sector PIO mode.
_DMA -> _UDMA, + cosmetic changes.
Ultra DMA still doesn't work.
Disable Ultra DMA for now, as it does not work.
Sync with HEAD.
Renamed pciide_pIIx_reg.h to pciide_piix_reg.h via repository copy,
as suggested by Soren S. Jorvan.
- sync with trunck
- don't try to set the drive's PIO mode if we don't know how to set it on the
  controller. This seems to confuse some 'intelligent' ISA controllers.
- sync with trunck
- for the piix, don't set timings for nonexistent drives.
- sync with trunck
- add a missing '~' when resetting the 32BIT flag to 0.
- don't try to set the PIO or DMA mode if we don't know how to set them
  on the controller. This seems to confuse some 'intelligent' isa controllers.
Sync with trunk.
If an error occured while setting up the drive, reset the drive's state
to 0.
Fix typos (from Soren S. Jorvan).
Print the minimum and recomended DMA timings if DEBUG_PROBE is defined.
Fix probe/attach for ATAPI or ATA-only kernels.
(XXX still 'brocken' in one way, will be worked out soon).
 - Fix timing settings for DMA: the controller was always set up to use
   DMA mode 0 (compatible).
 - The 2 Ultra-dma registers are in fact one 32-bit register.
   Change the macros and setup in a way it may now work (but still untested,
   thus not enabled by default).
 - For DMA mode 1, use a more efficient timing than the one suggested
   by intel.
Some work is still needed here to get ATAPI DMA working (should be done soon).
Fix confusion between binary and hex in DMA modes: 0x10 -> 0x02.