Reset in multiclock domain inheritance

Hi,
The following was the original code :
```scala
val reset = 
  if (x.component.hasExplicitReset)
    x.component._reset
  else if (x.clock != null)
    x.clock.getReset
  else if (x.component.hasExplicitClock)
    x.component.clock.getReset
  else
    x.component._reset
```
This code find the reset pin of each register. The bad side of this code is :
```scala
  else if (x.component.hasExplicitClock)
    x.component.clock.getReset
```
That's not recursive, i think that must find the first parrent component that has a explicite clock and take it. Actualy that juste look at the current component.
The effect of actual code is:
When you have a module with a explicite clock (with specific reset), and you instanciate a kind module that using default clock => the kind module use the parrent clock, but the kind reset is not the parrent clock's reset ! (because the actual code don't seach parent module's explicit clocks)

Maybe i have miss some case that made my file change proposition fail. Maybe the actual comportement is wanted. If it's any of that case, give me a feedback please.

Have a happy day