Add Verilog initialization statements for outports
Mark old "math.s" as deprecated -- the multi-byte addition operator doesn't exist
Fix read ready response, add missing signal initializations, improve diagnostics
Resolve issues with AXI4-Lite slave generation
Allow single values as the optional argument to the return macro
Add "Emit_IntegerValue" to "asmDef_9x8" class and use it in the .pushXX macros (to allow for named constants, etc.)
Add "pushByte" macro
Allow symbols for the length and improve the printout of the first instruction comment field
Fix comment and allow user-defined constants for the size argument
Add "IsConstant" method and improve parameter name extraction
Fix comment
Fix headers
Add lib/9x8/math.s and the associated test bench
Remove "uc.9x8" from ".gitignore"
Add missing "uc.9x8" to test bench