remove un needed merge code
ARM: 6998/2: kernel: use proper memory barriers for bitops

ARM: 6998/2: kernel: use proper memory barriers for bitops

Improve scalability by avoiding costly and unnecessary L2 cache sync
in handling bitops.

Change-Id: If6b9f52edbb597e3298227a13ed4e6edc629bf11
Signed-off-by: Heechul Yun <hyun@nvidia.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Maulik Mankad <maulik@ti.com>
mmc: decrease wakelock timeout
ARM: OMAP4: EMIF: implementation of errata i735 for PM timer

EMIF Power Management timer for Self Refresh will put the external SDRAM
in Self Refresh mode after the EMIF is idle for number of DDR clock cycles
that is set with REG_SR_TIM. The minimal value starts at 16 cycles.
However due to Errata i735, the minimal value is 512 DDR cycles as it is
required at OPP100 frequency.

Change-Id: If0748903580877aa4c1803f47e9134ee60c1dd75
Signed-off-by: Konstantyn Shlyakhovoy <x0155534@ti.com>
modified for tuna by faux123
ARM: 7632/1: spinlock: avoid exclusive accesses on unlock() path

When unlocking a spinlock, all we need to do is increment the owner
field of the lock. Since only one CPU can be performing an unlock()
operation for a given lock, this doesn't need to be exclusive.

This patch simplifies arch_spin_unlock to use non-exclusive accesses
when updating the owner field of the lock.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
HSMMC:Set disable timeout to 1ms

The disable timeout is reduced from 100ms to 1ms in order
to obtain aggressive power saving.

Cherry picked from p-android-omap-2.6.35 commit ID:
50df9d10a9b33c82ad02003686050b12b03d4dfe

Change-Id: Ieaa47d51396e7b92f6c1ba71e62900c58a05a26c
Signed-off-by: Madhusudhan Chikkature <madhu.cr@ti.com>
Signed-off-by: Viswanath Puttagunta <vishp@ti.com>
MMC: OMAP HSMMC: Enable Auto CMD12

Configure OMAP HSMMC module to support Auto CMD12.
This will increase throughput during multi-block
command operations as CMD12 does not have to be
explicitly sent each time by software intervention.
Instead, hardware will send CMD12 after desired
number of blocks are transferred.

Change-Id: I37bf31399c80531d9fd76baa736a59a118c769b0
Signed-off-by: Viswanath Puttagunta <vishp@ti.com>
mmc: OMAP HSMMC: Add cmd23 support

Add support for set block count, close ended transfer

Change-Id: Iab7386e1171a42ebdf55306fbf291a3e6dd85b40
Signed-off-by: Viswanath Puttagunta <vishp@ti.com>
omap4-hsmmc : Adding ADMA support

Adds ADMA support for HSMMC controllers 1 & 2 on OMAP4
Ensure dma-sg list coming from block layer is unmapped after
every transfer completion.

Change-Id: I1b898f771a3119804920c5cd17ec9c4456c60916
Signed-off-by: Viswanath Puttagunta <vishp@ti.com>
Signed-off-by: Kishore Kadiyala <kishore.kadiyala@ti.com>
Signed-off-by: David Taylor <x0158378@ti.com>
mmc: omap: align adma and dma table entries

mmc->max_segs to core layer was set to 1024, but
adma table entry could only hold 512 entries. Increase
adma table entry size to 1024 from 512 to avoid mismatch.

Also set max_blk_count, max_req_size to what adma can
handle.

Change-Id: I8e08ee39bfa966bdf8a6c4374aea82b34fedcc62
Signed-off-by: Viswanath Puttagunta <vishp@ti.com>
mmc: omap: Increase number of blks we can handle

The above block layer is doing a "min" of max_req_size
and max_blk_count*512 before submitting each request.

As a result, the maximum size of request we are getting
is only 120*512 = 60KB even though each line in the
ADMA table can handle can handle that data alone.

So, we increase the max_blk_count we can handle. Also,
note that worst case is when above block layer gives
us 512 segments, in which there are 511 single block
entries, but one large block that is of size
mmc->max_req_size - (511*512) bytes.

In this case, we use the reserved 512 table entries
to break up the large request. Also adjust the
max_segs accordingly.

Change-Id: I733effdebea94f51a49bbf323950529afbb00dc4
Signed-off-by: Viswanath Puttagunta <vishp@ti.com>
omap-hsmmc: Implementation of i761 errata

Errata description:
Due to a bad behavior of an internal signal, the Card Error interrupt bit
MMCHS_STAT[28] CERR may not be set sometimes when an error occurred in the
card response.

Workaround:
After responses of type R1/R1b for all cards and responses of type R5/R5b/R6
for SD and SDIO cards, software must read two registers: MMCHS_RSP10 and
MMCHS_CSRE. When a MMCHS_CSRE[i] bit is set to 1, if the corresponding bit at
the same position in the response MMCHS_RSP10[i] is set to 1, the host
controller indicates a card error and software should proceed in the same way
as if a CERR interrupt would have been detected in the MMCHS_STAT register.

Note:
This errata is applicable for omap44xx.

Change-Id: Ib024bfb0624df04b7d6c61c129cbd9a34f919814
Signed-off-by: Semen Protsenko <semen.protsenko@ti.com>
Force disable dsscomp debug
dsscomp: missing ifdef
timekeeping: Fix time moving backwards" -> https://github.com/Xmister/endeavoru-jb-crc-3.1.10/commit/1d86a5aa111fdd8af5ab44875d0fd8e7926ac696
dsscomp/device.c: fix warning defined but not used
gralloc.c: Fix int i unused var
OMAP:DSS2: Fix FIFO threshold calculation

    Calculated low-threshold value did not seem to work for
    the case of 1 > LineSize/MemoryLineBufferSize > 1/2.  Increased
    calculated value to avoid FIFO THRESHOLD UNDERFLOW errors.

    Change-Id: I60c7fa25de8737ef984bd1506cd70f1d39736acb
    Signed-off-by: Lajos Molnar <molnar@ti.com>

Rebased on latest c-model calculation fixes.

Change-Id: Icf086e71cf70385a0eaf6dbafe8377da92d053ba
Signed-off-by: Girish S G <girishsg@ti.com>
OMAP: DSS2: Fix callback completion issue in mgr->blank

Uncommitted callbacks were not completed yet eclipsed in mgr->blank.

Also fixed mgr index in ECLIPSED_CACHE callback.
This patch is co-authored with Muralidhar Dixit <murali.dixit@ti.com>

Change-Id: Ia20b79e9a6308441423d9900469e0c4adfc30eee
Signed-off-by: Lajos Molnar <lajos@ti.com>
Signed-off-by: Muralidhar Dixit <murali.dixit@ti.com>
OMAP4: DSS: Fix to correct the manager index for VSYNC irq handler

Patch to fix the Manager id in dss_completion_irq_handler.
DSSCOMP is expecting the manager id 1 to be mapped to HDMI display.
This patch fixes the DSSCOMP_STATE_DISPLAYED callback in DSSCOMP.

Change-Id: I0aab3e494cb305d75a64fabc4cd6919def636285
Signed-off-by: Muralidhar Dixit <murali.dixit@ti.com>
Signed-off-by: Varadarajan Charulatha <charu@ti.com>