ARM: dts: Enable additional GDSC collapse modes based on HW version

8974v2.2 supports additional collapse modes for Oxili, Venus,
and MDSS. Move the device-tree parameters that disable the modes
to version-specific files. Some MDSS collapse modes should still
remain disabled, even on v2.2.  All collapse modes are supported
on 8974Pro.

Change-Id: Ic9f1c057d16042d9a9c339dc5786cf35301169f0
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
ARM: dts: msm: modify memory reservation requirements for tmc-etr on 8974

The CoreSight TMC-ETR driver is modified to meet its coherent memory
allocation requirement using dma_alloc_coherent api instead of custom
allocate_contiguous_ebi function. Add support to the device tree to
specify this memory requirement.

Also retain the dt entry to allocate contiguous memory via
allocate_contiguous_ebi api until the corresponding driver changes go
in to prevent breaking TMC-ETR functionality.

Change-Id: I67b4813ab45d520311765500513ea265fb33188e
Signed-off-by: Aparna Das <adas@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
ARM: dts: msm: modify memory reservation requirements for tmc-etr on 9625

The CoreSight TMC-ETR driver now meets its coherent memory allocation
requirement using dma_alloc_coherent api instead of custom
allocate_contiguous_ebi function. Add support to the device tree to
specify this memory requirement.

Also retain the dt entry to allocate contiguous memory via
allocate_contiguous_ebi api until the corresponding driver changes go
in to prevent breaking TMC-ETR functionality.

Change-Id: I7e6288ad8a7c7583636ef221888e1774ba40d3ba
Signed-off-by: Aparna Das <adas@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
ARM: dts: msm: modify memory reservation requirements for tmc-etr on 8226

The CoreSight TMC-ETR driver now meets its coherent memory allocation
requirement using dma_alloc_coherent api instead of custom
allocate_contiguous_ebi function. Add support to the device tree to
specify this memory requirement.

Also retain the dt entry to allocate contiguous memory via
allocate_contiguous_ebi api until the corresponding driver changes go
in to prevent breaking TMC-ETR functionality.

Change-Id: I0aaab3aa2d79aac0c8cc523fe33e00ca55e0fac7
Signed-off-by: Aparna Das <adas@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
ARM: dts: msm: modify memory reservation requirements for tmc-etr on 8610

The CoreSight TMC-ETR driver now meets its coherent memory allocation
requirement using dma_alloc_coherent api instead of custom
allocate_contiguous_ebi function. Add support to the device tree to
specify this memory requirement.

Also retain the dt entry to allocate contiguous memory via
allocate_contiguous_ebi api until the corresponding driver changes go
in to prevent breaking TMC-ETR functionality.

Change-Id: I96785e3f876b1745ed84610cd2d85a1756bf671c
Signed-off-by: Aparna Das <adas@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
ARM: dts: msm: remove contiguous etr memory reservation support for 8974

The TMC driver now uses dma_alloc_coherent api to allocate contiguous
memory instead of allocate_contiguous_ebi when configured for ETR. This
eliminates need to specify EBI memory reservation requirement, remove
the same from dt.

Change-Id: I689613002b65e7c84938f89ce9794d2a165d9aeb
Signed-off-by: Aparna Das <adas@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
ARM: dts: msm: remove contiguous etr memory reservation support for 9625

The TMC driver now uses dma_alloc_coherent api to allocate contiguous
memory instead of allocate_contiguous_ebi when configured for ETR. This
eliminates need to specify EBI memory reservation requirement, remove
the same from dt.

Change-Id: Ief2aefb02f6dbdec6e5d65f76f6769baa9899650
Signed-off-by: Aparna Das <adas@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
ARM: dts: msm: remove contiguous etr memory reservation support for 8226

The TMC driver now uses dma_alloc_coherent api to allocate contiguous
memory instead of allocate_contiguous_ebi when configured for ETR. This
eliminates need to specify EBI memory reservation requirement, remove
the same from dt.

Change-Id: I77f4bf41372311b87c3d8bb4dc0fdc1a989c750c
Signed-off-by: Aparna Das <adas@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
ARM: dts: msm: remove contiguous etr memory reservation support for 8610

The TMC driver now uses dma_alloc_coherent api to allocate contiguous
memory instead of allocate_contiguous_ebi when configured for ETR. This
eliminates need to specify EBI memory reservation requirement, remove
the same from dt.

Change-Id: I269be8e8d3ecfa10e5a26841e88d939c3be0248a
Signed-off-by: Aparna Das <adas@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
coresight: add lpae support for coresight tmc driver

Modify the CoreSight TMC driver for LPAE so that it can support
ETR physical addresses greater than 32 bits when LPAE is enabled.

Change-Id: I6db2c98c4db70262ab45f7ff11fe2a6846259f8a
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
coresight: Add support for byte counter interrupt feature

The CoreSight block can produce an interrupt on transfer of
programmed number of bytes to ETR-memory. Use this feature
to provide an interface to manage the byte counter value and
to collect a continuous data stream from userspace.

Change-Id: Ic00c9b19483be566d0f05005936b4a6ff7ab52f1
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
coresight: use dma_alloc_coherent for allocating tmc-etr memory

The CoreSight TMC driver when configured for ETR requires uncached
memory in RAM to which it routes trace data. In order to allocate
this memory replace existing allocate_contiguous_ebi api with
dma_alloc_coherent api which is the linux standard of allocating
memory.

Change-Id: I59f88009f2abed95fd9b81ea92a7d484b9d6b833
Signed-off-by: Aparna Das <adas@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
coresight: enable flush-on-flushin for periodic flush to usb

Periodic flushing for ETR to USB uses ETR flush-on-FLUSHIN
external input. Hence, enable flush-on-FLUSHIN by default when
enabling ETR to USB transfers and work around the manual flush
failure by skipping it during ETR to USB disable. Adjust the
periodic flush threshold to the maximum value in order to
reduce the overhead when there is no data to be transferred.

CRs-Fixed: 461885
Change-Id: Ie3a1bbc80e017f187af56fcfdfb52297ba9aa72d
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
ARM: dts: msm: remove ebi cache dump reservation for 8974

The cache dump driver no longer uses the deprecated ebi memory
reservation api to reserve memory. As such, remove the
reservation from the device tree.

Change-Id: Ib016094da95c0dbc4520b9e3ed657487b180c853
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
msm: msm_bus: Change priority overrides based on master configuration

When BIMC master enables BKE (in limiter mode), priority override
should be disabled since master is getting limited bandwidth.
However when BKE is disabled, make sure priority overrides are enabled
if master is in fixed mode.
Also enable the bke bit as part of switching QOS modes.

Change-Id: I318b3542f3f5da5685d5641701e0b6c8fc64732c
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
Signed-off-by: Sagar Dharia <sdharia@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
msm: msm_bus: Changes for QOS computation at BIMC

Modify the computation of dynamic QOS parameters for BIMC. The bandwidth
paramter was incorrectly assumed to be in beats/s, it is infact in bytes/s
so there is no need to take bus width into account.
Also change resolution for statically prgrammed grant period to nano second
from micro second since each tick of the QOS clock is in the nano second
range.

Change-Id: Iad9ebc7837b769f8cd9c4215cb102f6916c0845d
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
Signed-off-by: Amir Vajid <avajid@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
ARM: dts: msm: Remove dual configuration for CPU on msm8974

Remove the dual configuration for CPU master on msm8974. The original
intent of this feature was to overcome some bus limitations in certain
usecases. However new desgin impovements have made this feature requirement
obsolete.

Change-Id: Ia0e61a59252c3f90fd32054fe1a5a9297afbc89c
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
ARM: 7693/1: mm: clean-up in order to reduce to call kmap_high_get()

In kmap_atomic(), kmap_high_get() is invoked for checking already
mapped area. In __flush_dcache_page() and dma_cache_maint_page(),
we explicitly call kmap_high_get() before kmap_atomic()
when cache_is_vipt(), so kmap_high_get() can be invoked twice.
This is useless operation, so remove one.

v2: change cache_is_vipt() to cache_is_vipt_nonaliasing() in order to
be self-documented

Change-Id: I36e5a63fdae158d9e7562f564f7e593b351f6960
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Joonsoo Kim <iamjoonsoo.kim@lge.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Git-commit: dd0f67f4747797f36f0c6bab7fed6a1f2448476d
Git-repo: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/
Signed-off-by: Chintan Pandya <cpandya@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
ARM: 7735/2: Preserve the user r/w register TPIDRURW on context switch and fork

Since commit 6a1c53124aa1 the user writeable TLS register was zeroed to
prevent it from being used as a covert channel between two tasks.

There are more and more applications coming to Windows RT,
Wine could support them, but mostly they expect to have
the thread environment block (TEB) in TPIDRURW.

This patch preserves that register per thread instead of clearing it.
Unlike the TPIDRURO, which is already switched, the TPIDRURW
can be updated from userspace so needs careful treatment in the case that we
modify TPIDRURW and call fork(). To avoid this we must always read
TPIDRURW in copy_thread.

Change-Id: Ib1e25be7b9faa846ba5335aad2574e21a1246066
Signed-off-by: André Hentschel <nerv@dawncrow.de>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Git-commit: a4780adeefd042482f624f5e0d577bf9cdcbb760
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[joonwoop@codeaurora.org: fixed merge conflict]
CRs-fixed: 561044
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>

Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
ARM: poison the vectors page

Fill the empty regions of the vectors page with an exception generating
instruction.  This ensures that any inappropriate branch to the vector
page is appropriately trapped, rather than just encountering some code
to execute.  (The vectors page was filled with zero before, which
corresponds with the "andeq r0, r0, r0" instruction - a no-op.)

Change-Id: I74c0105a2bcb3b78d9fc8b105a05c0fc269ba400
Cc: <stable@vger.kernel.org>
Acked-by Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Git-commit: f928d4f2a86f46b030fa0850385b4391fc2b5918
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
CRs-fixed: 561044
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>

Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>