ASoC: wcd9310: Fix DMIC current leakage after disable

Observed after disabling DMIC path, some DMICs observe
power leakage of around 2mA and affecting power numbers.
This happens due to the DMIC clock runs off MCLK. 2 Stage
of Dividers are used to  generate various DMIC Clock Freq.
Since the SW Enable/Disabling is async to MCLK, the Divider
will either hold the last stage 0 or 1.
Manually force the digital mic clock pin to GPIO mode from
functional mode through the TLMM mux option and force the value
of DMIC voltage to 0V. This will avoid any current leakage.

CRs-Fixed: 504468
Change-Id: I720fadda77b59454feb1a64d0c4951a6c09de66c
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
Merge "msm_fb: display: Add compulsory wait after DTV's TG is disabled."
msm: kgsl: Set alignment to 0 when low on mapped memory

If CPU map returns error due to low memory then we need to set
the alignment to 0 and instead of setting it to PAGE_OFFSET. This
is because we then simply search of a free memory gap at page
boundary and disrerard alignment requirement since memory is
low.

Change-Id: I828f5d0120d6d530e0e8857bcd96c9d5f266da10
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
msm: kgsl: Set proper pagetable address immediately after recovery

Update the MMU with proper pagetable address immediately after
recovery to avoid any translations with old pagetable.

Change-Id: Ib929598363e48a42b8ae174ed9718402541f5b09
Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
USB: EHCI:  Ensure 10 msec delay between bus states

According to EHCI specification, software must wait for at least 10 msec
after a port indicates that it is suspended before initiating a port
resume.  The current code uses jiffies and fails to give the delay if
suspend and resume happens at the timer tick boundaries.

The correct implementation would be ensuring this delay by using hrtimers
or ktime_get().  This involves changing many drivers.  Hence workaround
it by increasing the state change delay to 2 jiffies.

CRs-Fixed: 521047
Change-Id: I703210cca83d649d1b253e971dfba8f62c6ccb8c
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
perf: Treat attr.config as u64 in perf_swevent_init()

Trinity discovered that we fail to check all 64 bits of
attr.config passed by user space, resulting to out-of-bounds
access of the perf_swevent_enabled array in
sw_perf_event_destroy().

Introduced in commit b0a873ebb ("perf: Register PMU
implementations").

Signed-off-by: Tommi Rantala <tt.rantala@gmail.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: davej@redhat.com
Cc: Paul Mackerras <paulus@samba.org>
Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Patch-mainline: linux-kernel @ 04/13/13, 19:49
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.com>
msm: kgsl: Use the kmalloc/vmalloc trick for the sharedmem page array

It was previously assumed that most GPU memory allocations would be
small enough to allow us to fit the array of page pointers into one
or two pages allocated via kmalloc.  Recent reports have proven
those assumptions to be wrong - allocations on the order of 32MB will
end up trying to get 8 pages from kmalloc and 8 contiguous pages
on a busy system are a rare beast indeed.

So use the usual kmalloc/vmalloc trick instead - use kmalloc for the
page array when we can and vmalloc if we can't.

CRs-fixed: 513469
Change-Id: Ic0dedbad0a5b14abe6a8bd73342b3e68faa8c8b7
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Merge "perf: Treat attr.config as u64 in perf_swevent_init()"
msm: 8064-pmic: Update the maximum current supported by LEDs

LEDs on 8064 can support 12mA. Update the platform data
for LED to reflect the same.

CRs-fixed: 514882
Change-Id: I012051f63e39f90123373c78e4280bf008e1bbea
Signed-off-by: Mohan Pallaka <mpallaka@codeaurora.org>
gpu: ion: Free the sgtable for CMA based heaps

When an sgtable is allocated with sg_alloc_table, the table needs
to be destroyed in addition to being freed. Destroy the sgtable
when freeing the associated memory.

Change-Id: Iedba81146ba453070790f071848f86826f7eec9c
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Srinivasarao P <spathi@codeaurora.org>
mmc: core: Fix MMC clock scaling in case of tuning failure

When the clock scaling state is changed from MMC_LOAD_LOW to
MMC_LOAD_HIGH, the clocks are first scaled up and then tuning
is performed. But in case of tuning failure, the current code
does nothing but still retain the previous clock scale stats
(state and curr_freq within struct clk_scaling). Hence, correct
it to scale down the clocks in case of tuning failure so that
clock scaling stats reflect the correct status. This also helps
proceed with data transfers at lower clock rate in such cases.

Change-Id: I7e9379d1e3ddc863132af31019604c22a42f8d59
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
msm: msm_bus: Add NULL pointer check

This patch protects the bus driver against clients who try to
update requests without registering the client

Change-Id: Ie740844218dbabe5fca098798c461590aba42e97
CRs-Fixed: 459651
Signed-off-by: Gagan Mac <gmac@codeaurora.org>
msm: spm: modify power collapse seq for kraitv3

High sleep current observed due to L2 cache not going into
power collapse in special cases.

While analyzing, a timing issue was found that can manifest itself when the
clamp signal is asserted during the Krait CPU1 power collapse sequence.
When it occurs, the issue causes an L2 FIFO to falsely believe that it
has data to return to CPU1 when it does not.The condition isnt detected until
later when CPU0 and the L2 attempt to collapse.

This condition keeps the L2 from going idle which keeps it from power
collapsing after both CPUs have collapsed.  This in turn prevents the
RPM from enabling a system low power state (VDD minimization).
The issue is likely process/temp/voltage dependent.

HW team recommended a workaround, the details are as below.

Add commands to the Krait CPU power collapse SPM sequences to assert
Krait CPU reset prior to asserting the CPU clamp signal and de-assert
CPU reset after the CPU clamp is asserted.
Since the CPU clocks are gated (by the first SPM command in the
sequence), and the clamp is applied, the Krait CPU will do nothing
when its reset is de-asserted.

The workaround involves changing both CPU power collapse SPM sequences
(Power Collapse with and without RPM notification).

CRs-fixed: 518750
Change-Id: I62c76f49a96a8cb6ecf67733ae9a7ff1a79a76f7
Signed-off-by: Venkat Devarasetty <vdevaras@codeaurora.org>
Merge "USB: EHCI:  Ensure 10 msec delay between bus states"
Merge "msm: 8064-pmic: Update the maximum current supported by LEDs"
Merge "msm: msm_bus: Add NULL pointer check"
Merge "msm: spm: modify power collapse seq for kraitv3"
Merge "HSIC: Add support for product id 9075"
Merge "usb: ks_bridge: Add efs sync support for PID 0x9075"
power: pm8921-charger: Add delay after turning on D0 (TCXO) clock

On APQ8064, TCXO cannot be turned off before its warm-up period (4ms).
This is not required on the platform which have a CXO. Add a warm-up
delay after turning on D0 (which turns on the TCXO).

Change-Id: I252372c35a9fdfaf4a9fade1594936b05c1b5745
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>