Fix indentation
Move up assertion
Interchange input and output, it's confusing otherwise.
Now, traffic generation also makes sense. Earlier, we were generating
a random input port for every output port. It should be the other way
around, otherwise even 2 operations per tick for every memory bank
is sufficient.
Do not call front if queue is empty!!
Do not generate cells where the input and outport ports are identical
Get rid of bank_cursor_ member variable.
Assert that you have no loopback cells.
Add accessor for mem_ops_per_tick()
Implement algorithm from Appendix A.A of
"Routers with a single stage of buffering"
by Iyer et al SIGCOMM 2002.
Update unittests, thankfully 2 operations per tick fails now.