Adding gitignore file for Synopsys VCS simulator.

Synopsys VCS is a simulator that enables to analyze, compile and simulate Verilog, VHDL, mixed-HDL, SystemVerilog, OpenVera and SystemC design descriptions.  A copy of the User Guide can be downloaded from here:  http://users.ece.utexas.edu/~patt/10s.382N/handouts/vcs.pdf
There are a bunch of files and directories that get created as a result of the compilation of any given hardware design.  We typically don't care about those auto-generated files, nor we want them to be part of our version control system.