media: xilinx: Add Video Timing Controller driver

The Video Timing Controller (VTC) includes a timing detector and/or a
timing generator. Only the generator is currently supported.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
media: xilinx: tpg: Add VTC support

When configured in pattern generation (non-passthrough) mode the TPG
requires a VTC generator to supply timing information. Request the VTC
if specified in the device tree and configure it when starting and
stopping the stream.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
[HACK] arm: dts: zynq-zc706: Boot over NFS

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
[HACK] adv7604: Temporarily hardcode platform data

Until we have proper devicetree support for the adv7604 hardcode the platform
data to those required for the IMAGEON board.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
[HACK] adv7604: Implement format pad operations

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
[HACK] media: xilinx: tpg: Add video timing mux support

The current version of the TPG core has no video timing input interface
but requires video timings to be supplied through its AXI stream slave
interface when generating a test pattern.

The VDF design thus instantiates a video timing mux in front of the
video 2 AXI stream core. The mux is controlled through a GPIO, which
needs to be controlled by the TPG driver.

Future versions of the TPG core will have a video timing input
interface, removing the need for GPIO mux control.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
[HACK] arm: dts: zc706-vdf: Add video timing mux GPIO to TPG

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
media: xilinx: vtc: Add video clock support

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
arm: dts: zc706-vdf: Add clock property to VTC

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
v4l: Add pad-level DV timings subdev operations

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
v4l: Improve readability by not wrapping ioctl number #define's

Wrapping the #define's at a 80 columns boundary just obfuscates the
code. Don't do that.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
v4l: Add support for DV timings ioctls on subdev nodes

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
adv7604: Add sink pads

The ADV7604 has sink pads for its HDMI and analog inputs. Report them.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
adv7604: Add pad-level DV timings support

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
media: xilinx: tpg: Setup controls at probe time

Write the default value of all controls to the hardware at probe time to
make sure the hardware and software configurations match.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
[HACK] media: xiling: tpg: Raise vertical blanking

This lowers the frame rate to around 60fps with the VDF design.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
[DEBUG] media: xilinx: vtc: Add interrupt support

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
[DEBUG] media: xilinx: Add register read/write debug to TPG and VTC

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
[DEBUG] media: xilinx: Add debugging messages

Trace VTC and TPG start/stop and print the TPG status when VTC
interrupts occur.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
[DEBUG] dma: xilinx: vdma: Add debugging messages

Print all register accesses and trace several operations.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>