[x]  Need thermal reliefs on thru-hole plane connections (many places)
[x] Also to bottom layer 5V plane
[x] Need thermal reliefs on SMT connections to bottom layer in 5V area
[x] The PWR_EN trace going to U5-1 probably doesn’t need to take such a snaky path
[x] Add DDS board outline to silkscreen
[x] Guard GND traces around DDS CLKs
[x] Clean up bottom silk.
[x] Alter rules to fit Advanced PCB's
[x] Confirm the clock pair from the ADC goes to a clock-capable
    input on the FPGA. Notes:
		- Up to 8 clocks can be brought in on a Bank
		- Use IBUFDS resources.
		- use IDDR  input block to do double datarate sampling
		-- Use SAME_EDGE_PIPELINED for best performance.
[x] Update SMA connector footprints.