Delayed JTAG reset by 4ms to avoid conflict when programming DCFEB FPGA
Increased delay to send JTAG reset to 24ms
Changed polarity of BXRST to recover BX in headers, fixed OTMB FIFO reset, masked FIFO enables until first reset
Reset BX at 3564, delayed EOF_DATA to allow for 4-word DCFEB packets
Added BX_DLY and the 2772 offset to sync the DMB and ODMB BX